AM486DX5-133W16BHC AMD (ADVANCED MICRO DEVICES), AM486DX5-133W16BHC Datasheet - Page 44

• Manufacturer Part Number: AM486DX5-133W16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX5-133W16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.45V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

44
Note:
Interrupts from INT and NMI are disabled on SMM entry.
The following is a summary of the key features in the
SMM environment:
6.7
The processor begins execution of the SMI handler at
offset 8000h in the CS segment. The CS Base is initially
30000h, as shown in Table 13.
The CS Base can be changed using the SMM Base
relocation feature . When the SMI handler is invoked,
the CPU’s PE and PG bits in CR0 are reset to 0. The
processor is in an environment similar to Real mode,
but without the 64-Kbyte limit checking. However, the
default operand size and the default address size are
set to 16 bits. The EM bit is cleared so that no exceptions
are generated. (If the SMM was entered from Protected
mode, the Real mode interrupt and exception support
is not available.) The SMI handler should not use float-
ing-point unit instructions until the FPU is properly de-
tected (within the SMI handler) and the exception
support is initialized.
Table 12. SMM Initial CPU Core Register Settings
Register
General Purpose
Registers
EFLAGS
CR0
DR6
DR7
GDTR, LDTR,
IDTR, TSSR
EIP
Real mode style address calculation
4-Gbyte limit checking
IF flag is cleared
NMI is disabled
TF flag in EFLAGS is cleared; single step traps are
disabled
DR7 is cleared; debug traps are disabled
The RSM instruction no longer generates an invalid
opcode error
Default 16-bit opcode, register, and stack use
All bus arbitration (HOLD, AHOLD, BOFF) inputs,
and bus sizing (BS8, BS16) inputs operate normally
while the CPU is in SMM
Executing System Management
Mode Handler
SMM Initial State
Unmodified
0000 0002h
Bits 0, 2, 3, and 31 cleared (PE, EM, TS,
and PG); rest unmodified
Unpredictable state
0000 0400h
Unmodified
0000 8000h
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
Notes:
1. The segment limit check is 4 Gbytes instead of the usual
2. The Selector value for CS remains at 3000h even if the
Because the segment bases (other than CS) are cleared
to 0 and the segment limits are set to 4 Gbytes, the
address space may be treated as a single flat 4-Gbyte
linear space that is unsegmented. The CPU is still in
Real mode and when a segment selector is loaded with
a 16-bit value, that value is then shifted left by 4 bits and
loaded into the segment base cache.
In SMM, the CPU can access or jump anywhere within
the 4-Gbyte logical address space. The CPU can also
indirectly access or perform a near jump anywhere with-
in the 4-Gbyte logical address space.
6.7.1 Exceptions and Interrupts with System
When the CPU enters SMM, it disables INTR interrupts,
debug, and single step traps by clearing the EFLAGS,
DR6, and DR7 registers. This prevents a debug appli-
cation from accidentally breaking into an SMI handler.
This is necessary because the SMI handler operates
from a distinct address space (SMRAM) and the debug
trap does not represent the normal system memory
space.
For an SMI handler to use the debug trap feature of the
processor to debug SMI handler code, it must first en-
sure that an SMM-compliant debug handler is available.
The SMI handler must also ensure DR3–DR0 is saved
to be restored later. The debug registers DR3–DR0 and
DR7 must then be initialized with the appropriate values.
For the processor to use the single step feature of the
processor, it must ensure that an SMM-compliant single
step handler is available and then set the trap flag in the
EFLAGS register. If the system design requires the pro-
cessor to respond to hardware INTR requests while in
SMM, it must ensure that an SMM-compliant interrupt
handler is available, and then set the interrupt flag in the
Segment
Register
CS
64 Kbyte.
SMBASE is changed.
GS
DS
ES
FS
SS
Table 13. Segment Register Initial States
2
Management Mode
Selector
3000h
0000h
0000h
0000h
0000h
0000h
00000000h
00000000h
00000000h
00000000h
00000000h
30000h
Base
Attributes
expand up
expand up
expand up
expand up
expand up
expand up
16-bit,
16-bit,
16-bit,
16-bit,
16-bit,
16-bit,
4 Gbytes
4 Gbytes
4 Gbytes
4 Gbytes
4 Gbytes
4 Gbytes
Limit
1