IDT74SSTVF16859PA IDT, Integrated Device Technology Inc, IDT74SSTVF16859PA Datasheet

IDT74SSTVF16859PA

Manufacturer Part Number

IDT74SSTVF16859PA

Description

Manufacturer

IDT, Integrated Device Technology Inc

Datasheet

1.IDT74SSTVF16859PA.pdf (7 pages)

Specifications of IDT74SSTVF16859PA

Logic Family

SSTV

Logical Function

Registered Buffer

Number Of Elements

Number Of Bits

Number Of Inputs

Number Of Outputs

High Level Output Current

-16mA

Low Level Output Current

16mA

Package Type

TSSOP

Propagation Delay Time

2.9ns

Operating Supply Voltage (typ)

2.5V

Operating Supply Voltage (max)

2.7V

Operating Supply Voltage (min)

2.3V

Clock-edge Trigger Type

Posit/Negat-Edge

Polarity

Non-Inverting

Technology

CMOS

Frequency (max)

220(Min)MHz

Mounting

Surface Mount

Pin Count

Operating Temp Range

0C to 70C

Operating Temperature Classification

Commercial

Lead Free Status / Rohs Status

Not Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

IDT74SSTVF16859PA8

Manufacturer:

IDT

Quantity:

10 000

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

IDT74SSTVF16859PAG

Manufacturer:

IDT

Quantity:

1 402

Company:

H&T Electronics

Part Number:

IDT74SSTVF16859PAG

Quantity:

646

Current page: 1 of 7
Download datasheet (76Kb)

FEATURES:

• 1:2 register buffer

• Meets or exceeds JEDEC standard SSTVF16859

• 2.3V to 2.7V Operation for PC1600, PC2100, and PC2700

• 2.5V to 2.7V Operation for PC3200

• SSTL_2 Class I style data inputs/outputs

• Differential CLK input

• RESET control compatible with LVCMOS levels

• Latch-up performance exceeds 100mA

• ESD >2000V per MIL-STD-883, Method 3015; >200V using

• Available in 56 pin VFQFPN and 64 pin TSSOP packages

APPLICATIONS:

• Along with CSPT857C, Zero Delay PLL Clock buffer, provides

COMMERCIAL TEMPERATURE RANGE

FUNCTIONAL BLOCK DIAGRAM

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

IDT74SSTVF16859

13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O

complete solution for DDR1 DIMMs

machine model (C = 200pF, R = 0)

2003 Integrated Device Technology, Inc.

RESET

CLK

REF

13-BIT TO 26-BIT REGISTERED

BUFFER WITH SSTL I/O

TO 12 OTHER CHANNELS

DESCRIPTION:

2.3V-2.7V V

supports low standby operation. All data inputs and outputs are SSTL_2

level compatible with JEDEC standard for SSTL_2.

power-up phase. RESET, which can be operated independent of CLK and

CLK, must be held in the low state during power-up in order to ensure

predictable outputs (low state) before a stable clock has been applied.

registers, and force all outputs to a low state, before a stable clock has been

applied. With inputs held low and a stable clock applied, outputs will remain

low during the Low-to-High transition of RESET.

The SSTVF16859 is a 13-bit to 26-bit registered buffer designed for

RESET is an LVCMOS input since it must operate predictably during the

RESET, when in the low state, will disable all input receivers, reset all

for PC1600 - PC2700 and 2.5V-2.7V V

COMMERCIAL TEMPERATURE RANGE

IDT74SSTVF16859

AUGUST 2003

for PC3200, and

DSC-6194/14

Related parts for IDT74SSTVF16859PA

IDT74SSTVF16859PA Summary of contents

Page 1

IDT74SSTVF16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: • 1:2 register buffer • Meets or exceeds JEDEC standard SSTVF16859 • 2.3V to 2.7V Operation for PC1600, PC2100, and PC2700 • 2.5V to 2.7V Operation for PC3200 • SSTL_2 ...

Page 2

IDT74SSTVF16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O PIN CONFIGURATIONS GND 12B Q 11B Q 10B Q ...

Page 3

IDT74SSTVF16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O PIN DESCRIPTION Pin Names Description Data Output 1 13 GND Ground V Output-stage drain power voltage DDQ V Logic power voltage DD RESET Asynchronous reset input - resets ...

Page 4

IDT74SSTVF16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR PC3200 Following Conditions Apply Unless Otherwise Specified: Operating Condition 0°C to +70° Symbol Parameter V Control Inputs ...

Page 5

IDT74SSTVF16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE Symbol Parameter Clock Frequency CLOCK tw Pulse Duration, CLK, CLK HIGH or LOW t Differential Inputs Active Time (1) ACT t Differential Inputs ...

Page 6

IDT74SSTVF16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O TEST CIRCUITS AND WAVEFORMS FOR PC1600 - PC2700, V FOR PC3200 2.6V ± 0.1V DD LVCMOS RESET Input t INACT I 10% DD (see note 2) ...

Page 7

IDT74SSTVF16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O ORDERING INFORMATION XX XXX IDT74SSTVF Family Device Type XX XX Package Process Blank PA Thin Shrink Small Outline Package PAG TSSOP - Green NL Thermally Enhanced Plastic Very Fine Pitch Quad ...

Related keywords

IDT74SSTVF16859PA datasheet
IDT74SSTVF16859PA data sheet
IDT74SSTVF16859PA pdf datasheet
IDT74SSTVF16859PA component
IDT74SSTVF16859PA part
IDT74SSTVF16859PA distributor
IDT74SSTVF16859PA RoHS
IDT74SSTVF16859PA datasheet download