ADSP-21266SKSTZ-1B Analog Devices Inc, ADSP-21266SKSTZ-1B Datasheet - Page 6

• Manufacturer Part Number: ADSP-21266SKSTZ-1B
• Manufacturer: Analog Devices Inc

Specifications of ADSP-21266SKSTZ-1B

• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 256KB
• Program Memory Size: 512KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Compliant

ADSP-21261/ADSP-21262/ADSP-21266
Table 5. Internal Memory Space (ADSP-21262/ADSP-21266)
Digital Application Interface (DAI)
The Digital application interface provides the ability to connect
various peripherals to any of the SHARC DSP’s DAI pins
(DAI_P20–1).
Connections are made using the signal routing unit (SRU,
shown in the block diagram
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with noncon-
figurable signal paths.
The DAI also includes six serial ports, two precision clock gen-
erators (PCGs), an input data port (IDP), six flag outputs and
six flag inputs, and three timers. The IDP provides an additional
input path to the ADSP-2126x core, configurable as either eight
channels of I
20-bit wide synchronous parallel data acquisition port. Each
data channel has its own DMA channel that is independent
from the ADSP-2126x’s serial ports.
For complete information on using the DAI, see the
ADSP-2126x SHARC DSP Peripherals Manual.
Serial Ports
The ADSP-2126x features six full duplex synchronous serial
ports that provide an inexpensive interface to a wide variety of
digital and mixed-signal peripheral devices such as the Analog
Devices AD183x family of audio codecs, ADCs, and DACs. The
serial ports are made up of two data lines, a clock, and frame
sync. The data lines can be programmed to either transmit or
receive and each data line has its own dedicated DMA channel.
Serial ports are enabled via 12 programmable and simultaneous
receive or transmit pins that support up to 24 transmit or 24
receive channels of audio data when all six SPORTs are enabled,
or six full duplex TDM streams of 128 channels per frame.
IOP Registers 0x0000 0000–0003 FFFF
Long Word (64 Bits)
Block 0 SRAM
0x0004 0000–0x0004 3FFF
Reserved
0x0004 4000–0x0005 7FFF
Block 0 ROM
0x0005 8000–0x0005 FFFF
Block 1 SRAM
0x0006 0000–0x0006 3FFF
Reserved
0x0006 4000–0x0007 7FFF
Block 1 ROM
0x0007 8000–0x0007 FFFF
2
S or serial data, or as seven channels plus a single
on Page
Extended Precision Normal or
Instruction Word (48 Bits)
Block 0 SRAM
0x0008 0000–0x0008 5555
Reserved
Block 0 ROM
0x000A 0000–0x000A AAAA
Block 1 SRAM
0x000C 0000–0x000C 5555
Reserved
Block 1 ROM
0x000E 0000–0x000E AAAA
1).
Rev. F | Page 6 of 44 | July 2009
Normal Word (32 Bits)
Block 0 SRAM
0x0008 0000–0x0008 7FFF
Reserved
0x0008 8000–0x000A FFFF
Block 0 ROM
0x000B 0000–0x000B FFFF
Block 1 SRAM
0x000C 0000–0x000C 7FFF
Reserved
0x000C 8000–0x000E FFFF
Block 1 ROM
0x000F 0000–0x000F FFFF
The serial ports operate at up to one-quarter of the DSP core
clock rate, providing each with a maximum data rate of
50M bits/sec for a 200 MHz core and 37.5M bits/sec for a
150 MHz core. Serial port data can be automatically transferred
to and from on-chip memory via a dedicated DMA. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit sig-
nals while the other SPORT provides two receive signals. The
frame sync and clock are shared.
Serial ports operate in four modes:
Left-justified sample pair mode is a mode where in each frame
sync cycle, two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over var-
ious attributes of this mode.
Each of the serial ports supports the left-justified sample-pair
and I
monly used by audio codecs, ADCs, and DACs) with two data
pins, allowing four left-justified sample-pair or I
(using two stereo devices) per serial port with a maximum of up
to 24 audio channels. The serial ports permit little-endian or
big-endian transmission formats and word lengths selectable
from 3 bits to 32 bits. For the left-justified sample pair and I
modes, data-word lengths are selectable between 8 bits and 32
bits. Serial ports offer selectable synchronization and transmit
modes as well as optional -law or A-law companding selection
on a per channel basis. Serial port clocks and frame syncs can be
internally or externally generated.
• Standard DSP serial mode
• Multichannel (TDM) mode
• I
• Left-justified sample pair mode
2
2
S protocols (I
S mode
2
S is an industry-standard interface com-
Short Word (16 Bits)
Block 0 SRAM
0x0010 0000–0x0010 FFFF
Reserved
0x0011 0000–0x0015 FFFF
Block 0 ROM
0x0016 0000–0x0017 FFFF
Block 1 SRAM
0x0018 0000–0x0018 FFFF
Reserved
0x0019 0000–0x001D FFFF
Block 1 ROM
0x001E 0000–0x001F FFFF
2
S channels
2
S