IDT70V9279S15PRF IDT, Integrated Device Technology Inc, IDT70V9279S15PRF Datasheet - Page 10

IDT70V9279S15PRF

Manufacturer Part Number
IDT70V9279S15PRF
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT70V9279S15PRF

Density
512Kb
Access Time (max)
15ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
28.5MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
15b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
220mA
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
128
Word Size
16b
Number Of Words
32K
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT70V9279S15PRF
Manufacturer:
IDT
Quantity:
100
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE
Timing Waveform of Read Cycle for Pipelined Output
(FT/PIPE
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = V
4. The output is disabled (High-Impedance state) by CE
5. Addresses do not have to be accessed sequentially since ADS = V
6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATA
7. "
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
are for reference use only.
X
" denotes Left or Right port. The diagram is with respect to that port.
ADDRESS
ADDRESS
DATA
DATA
IL
UB, LB
UB, LB
, CNTEN and CNTRST = V
CLK
R/
CE
CE
CLK
OUT
R/
CE
OE
CE
OUT
OE
W
W
0
1
"X"
"X"
0
1
(5)
(2)
(5)
(2)
= V
= V
t
t
t
t
SW
SB
SA
t
t
SC
t
t
SC
SB
SW
SA
An
IH
IL
An
)
t
t
t
)
t
t
HC
HB
HW
t
HA
t
t
HW
(3,7)
HC
HB
HA
(1 Latency)
(3,7)
IH
t
CH2
t
t
.
CH1
CKLZ
(1)
t
t
CYC2
CD1
t
CYC1
t
CKLZ
t
CL2
t
CL1
(1)
An + 1
An + 1
0
= V
Qn
IH
t
DC
IL
t
CD2
or CE
constantly loads the address on the rising edge of the CLK; numbers
OUT
6.42
1
for Qn + 2 would be disabled (High-Impedance state).
10
= V
IL
following the next rising edge of the clock. Refer to Truth Table 1.
An + 2
An + 2
Qn
Qn + 1
t
t
OHZ
DC
Industrial and Commercial Temperature Ranges
(1)
Qn + 1
t
t
OE
OLZ
t
OHZ
(1)
t
An + 3
t
t
t
An + 3
SC
SC
(4)
SB
(1)
SB
(6)
Qn + 2
t
t
t
t
HC
HB
HC
HB
t
DC
t
CKHZ
t
t
OE
OLZ
(1)
(1)
3743 drw 06
Qn + 2
3743 drw 07
(6)

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