71V35761S166BG

Manufacturer Part Number71V35761S166BG
ManufacturerIDT, Integrated Device Technology Inc
71V35761S166BG datasheet
 


Specifications of 71V35761S166BG

Density4.5MbAccess Time (max)3.5ns
Sync/asyncSynchronousArchitectureSDR
Clock Freq (max)166MHzOperating Supply Voltage (typ)3.3V
Address Bus17bPackage TypeBGA
Operating Temp Range0C to 70CNumber Of Ports1
Supply Current320mAOperating Supply Voltage (min)3.135V
Operating Supply Voltage (max)3.465VOperating Temperature ClassificationCommercial
MountingSurface MountPin Count119
Word Size36bNumber Of Words128K
Lead Free Status / Rohs StatusNot Compliant  
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128K x 36, 256K x 18 memory configurations
Supports high system speed:
Commercial:
– 200MHz 3.1ns clock access time
Commercial and Industrial:
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array
A
-A
Address Inputs
0
17
CE
Chip Enable
, CS
CS
Chip Selects
0
1
OE
Output Enable
GW
Global Write Enable
BWE
Byte Write Enable
BW
, BW
, BW
, BW
(1)
Individual Byte Write Selects
1
2
3
4
CLK
Clock
ADV
Burst Address Advance
ADSC
Address Status (Cache Controller)
ADSP
Address Status (Processor)
LBO
Linear / Interleaved Burst Order
ZZ
Sleep Mode
I/O
-I/O
, I/O
-I/O
Data Input / Output
0
31
P1
P4
V
, V
Core Power, I/O Power
DD
DDQ
V
Ground
SS
NOTE:
1. BW
and BW
are not applicable for the IDT71V35781.
3
4
©2000 Integrated Device Technology, Inc.
128K x 36, 256K x 18
3.3V Synchronous SRAMs
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
The IDT71V35761/781 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V35761/781 SRAMs contain write, data,
address and control registers. Internal logic allows the SRAM to generate
a self-timed write based upon a decision which can be left until the end of
the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V35761/81 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V35761/781 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array.
1
IDT71V35761
IDT71V35781
Input
Synchronous
Input
Synchronous
Input
Synchronous
Input
Asynchronous
Input
Synchronous
Input
Synchronous
Input
Synchronous
Input
N/A
Input
Synchronous
Input
Synchronous
Input
Synchronous
Input
DC
Input
Asynchronous
I/O
Synchronous
Supply
N/A
Supply
N/A
5301 tbl 01
DSC-5301/02

71V35761S166BG Summary of contents

  • Page 1

    ... The burst mode feature offers the highest level of performance to the system designer, as the IDT71V35761/81 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge ...

  • Page 2

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Symbol Pin Function I Address Inputs ADSC Address Status I (Cache Controller) ADSP Address Status I (Processor) ADV Burst Address I Advance BWE Byte Write Enable ...

  • Page 3

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect LBO ADV CLK ADSC ADSP 16/17 GW BWE Powerdown OE 36/18 I/O — I I/O — I Commercial and Industrial Temperature Ranges Burst CEN Sequence 2 Burst ...

  • Page 4

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Symbol Rating (2) V Terminal Voltage with TERM Respect to GND (3,6) V Terminal Voltage with TERM Respect to GND (4,6) V Terminal Voltage with TERM Respect to GND ...

  • Page 5

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect 100 DDQ DDQ DDQ I DDQ NOTES: 1. Pin 14 can either be directly connected Pins 38 and 39 can be either NC or connected ...

  • Page 6

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect DDQ I I DDQ DDQ DDQ NOTES: 1. Pin 14 can either be directly connected Pins 38 and 39 can be either NC or connected Pin 64 can be left unconnected and the device will always remain in active mode. ...

  • Page 7

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect DDQ I I DDQ DDQ DDQ I I DDQ DDQ I DDQ I DDQ I DDQ I DDQ NOTES can either be directly connected connected to an input voltage DD 2 ...

  • Page 8

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect ( I DDQ D I/O I DDQ E I/O I DDQ F I/O I DDQ G I/O I DDQ (1) ( I/O I DDQ K I/O I DDQ L I/O I DDQ M I/O I DDQ N I DDQ ( LBO ( ( DDQ D NC ...

  • Page 9

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Symbol Parameter |I | Input Leakage Current LI ZZ and LBO Input Leakage Current |I | LZZ |I | Output Leakage Current LO V Output Low Voltage OL V Output High Voltage ...

  • Page 10

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Operation Address Used cte d Cycle , cte d Cycle , cte d Cycle , cte d Cycle , cte d Cycle , Cycle , urst Exte rnal Re ad Cycle , urst Exte rnal ...

  • Page 11

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect GW Operation Read H Read H Write all Bytes L Write all Bytes H (3) Write Byte 1 H (3) Write Byte 2 H (3) Write Byte 3 H (3) Write Byte 4 H NOTES: 1 ...

  • Page 12

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Symbol Parameter t Clock Cycle Time CYC (1) Clock High Pulse Width t CH (1) Clock Low Pulse Width t CL Output Parameters t Clock High to Valid Data ...

  • Page 13

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges , 6.42 13 ...

  • Page 14

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges , 6.42 14 ...

  • Page 15

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges GW 6. ...

  • Page 16

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6. ...

  • Page 17

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6. ...

  • Page 18

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect CLK ADSP ADSC ADDRESS GW, BWE, BWx CE DATA OUT NOTES input is LOW, ADV is HIGH and LBO is Don't Care for this cycle. 2. (Ax) represents the data for address Ax, etc. ...

  • Page 19

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 19 ...

  • Page 20

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 20 ...

  • Page 21

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 21 ...

  • Page 22

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect IDT XXX Device Power Speed Package Type X Process/ Temperature Range Blank Commercial (0°C to +70°C) I Industrial (-40°C to +85°C) PF 100-pin Plastic Thin Quad Flatpack (TQFP) ...

  • Page 23

    ... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect 12/31/99 Pg 11, 19 04/04/00 Pg. 18 Pg. 4 06/01/00 Pg. 20 07/15/00 Pg. 7 Pg. 8 Pg. 20 10/25/00 Pg. 8 04/22/03 Pg.4 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 The IDT logo is a registered trademark of Integrated Device Technology, Inc ...