71V3577S75BG IDT, Integrated Device Technology Inc, 71V3577S75BG Datasheet - Page 11

• Manufacturer Part Number: 71V3577S75BG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 71V3577S75BG

• Density: 4.5Mb
• Access Time (max): 7.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 117MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: BGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 255mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 119
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

NOTES:
1. L = V
2. BW
3. Multiple bytes may be selected during the same cycle.
NOTES:
1. L = V
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
First Address
Second Address
Fourth Address
First Address
Second Address
Fourth Address
Third Address
Third Address
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
3
and BW
IL
IL
, H = V
, H = V
Write all Bytes
Write all Bytes
Write Byte 1
Write Byte 2
Write Byte 3
Write Byte 4
Operation
(1)
(1)
Read
Read
4
IH
IH
are not applicable for the IDT71V3579.
Sleep Mode
Operation
, X = Don’t Care.
Deselected
, X = Don’t Care.
Read
Read
Write
(3)
(3)
(3)
(3)
(2)
GW
H
H
L
H
H
H
H
H
OE
X
X
X
L
H
A1
A1
0
0
0
0
1
1
1
1
Sequence 1
Sequence 1
BWE
H
X
LBO
L
L
L
L
L
L
A0
A0
0
0
0
0
1
1
1
1
ZZ
H
6.42
L
L
L
L
LBO
11
BW
X
H
X
H
H
H
L
L
A1
A1
0
0
0
0
1
1
1
1
1
Sequence 2
Sequence 2
A0
A0
0
0
0
0
1
1
1
1
Commercial and Industrial Temperature Ranges
High-Z – Data In
BW
X
H
X
L
H
L
H
H
I/O Status
Data Out
2
High-Z
High-Z
High-Z
A1
A1
0
0
0
0
1
1
1
1
Sequence 3
Sequence 3
A0
A0
BW
0
0
0
0
1
1
1
1
X
X
H
L
H
H
L
H
3
A1
A1
0
0
0
0
1
1
1
1
Sequence 4
Sequence 4
Standby
Power
Active
Active
Active
Sleep
BW
X
X
H
L
H
H
H
L
4
5280 tbl 12
5280 tbl 13
5280 tbl 14
5280 tbl 15
A0
A0
0
0
0
0
1
1
1
1