ICS8521AYI-03 IDT, Integrated Device Technology Inc, ICS8521AYI-03 Datasheet
ICS8521AYI-03
Specifications of ICS8521AYI-03
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ICS8521AYI-03 Summary of contents
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G D ENERAL ESCRIPTION The ICS8521I- low skew, 1-to-9 Differential-to- LVHSTL Fanout Buffer . The ICS8521I-03 has two selectable clock inputs. Redundant clock pairs, CLK0, nCLK0 and CLK1, nCLK1 can accept most standard differential input levels. The clock ...
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ABLE IN ESCRIPTIONS ...
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T 3A ABLE ONTROL NPUT UNCTION ...
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BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Package Thermal Impedance, θ JA Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS ...
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T 4D. LVHSTL DC C ABLE HARACTERISTICS ...
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P ARAMETER 1.8V ± 0.2V 3.3V ± DDO LVHSTL GND = 0V 3.3V C /1. ORE UTPUT OAD nQx Qx nQy Qy t sk( UTPUT KEW nCLK0, nCLK1 CLK0, CLK1 ...
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IRING THE IFFERENTIAL NPUT TO Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias ...
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S E CHEMATIC XAMPLE This application note provides general design guide using ICS8521I-03 LVHSTL buffer. Figure 3A shows a schematic ex- ample of the ICS8521I-03 LVHSTL Clock buffer. In this example, 1. Ohm Ohm ...
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OWER ROUND AND YPASS APACITOR This section provides a layout guide related to power, ground and placement of bypass capacitors for a high-speed digital IC. This layout guide is a general recommendation. The actual board ...
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IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING V and V input requirements. Figures show PP CMR interface examples for the ...
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This section provides information on power dissipation and junction temperature for the ICS8521I-03. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8521I-03 is the sum of the core power plus the power ...
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Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVHSTL output driver circuit and termination are shown in Figure 5. F IGURE T o calculate worst case power dissipation into the ...
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ABLE VS IR LOW ABLE JA θ θ θ θ θ Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data ...
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ACKAGE UTLINE UFFIX ABLE θ θ θ θ ...
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ABLE RDERING NFORMATION ...
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8521AYI-03 D IFFERENTIAL R E ...
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We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...