A42MX24-PQ208 MICROSEMI, A42MX24-PQ208 Datasheet - Page 10

• Manufacturer Part Number: A42MX24-PQ208
• Manufacturer: MICROSEMI

Specifications of A42MX24-PQ208

• Family Name: 42MX
• Number Of Usable Gates: 36000
• Number Of Logic Blocks/elements: 912
• # Registers: 1410
• # I/os (max): 176
• Process Technology: 0.45um (CMOS)
• Operating Supply Voltage (typ): 3.3/5V
• Logic Cells: 912
• Device System Gates: 36000
• Propagation Delay Time: 2.5/1.8ns
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Routing Structure
The MX architecture uses vertical and horizontal routing
tracks to interconnect the various logic and I/O modules.
These routing tracks are metal interconnects that may be
continuous or split into segments. Varying segment
lengths allow the interconnect of over 90% of design
tracks to occur with only two antifuse connections.
Segments can be joined together at the ends using
antifuses to increase their lengths up to the full length of
the track. All interconnects can be accomplished with a
maximum of four antifuses.
Horizontal Routing
Horizontal routing tracks span the whole row length or
are divided into multiple segments and are located in
between the rows of modules. Any segment that spans
more than one-third of the row length is considered a
long horizontal segment. A typical channel is shown in
Figure
tracks are used for global clock networks and for power
and ground tie-off tracks. Non-dedicated tracks are used
for signal nets.
Vertical Routing
Another set of routing tracks run vertically through the
module. There are three types of vertical tracks: input,
output, and long. Long tracks span the column length of
the module, and can be divided into multiple segments.
Each segment in an input track is dedicated to the input
of a particular module; each segment in an output track
is dedicated to the output of a particular module. Long
segments are uncommitted and can be assigned during
routing. Each output segment spans four channels (two
above and two below), except near the top and bottom
of the array, where edge effects occur. Long vertical
tracks contain either one or two segments. An example
of vertical routing tracks and segments is shown in
Figure
Antifuse Structures
An antifuse is a "normally open" structure. The use of
antifuses to implement a programmable logic device
results in highly testable structures as well as efficient
programming algorithms. There are no pre-existing
connections; temporary connections can be made using
pass transistors. These temporary connections can isolate
individual antifuses to be programmed and individual
circuit structures to be tested, which can be done before
and after programming. For instance, all metal tracks can
be tested for continuity and shorts between adjacent
tracks, and the functionality of all logic modules can be
verified.
1 -4
40MX and 42MX FPGA Families
1-6. Within horizontal routing, dedicated routing
1-6.
v6.1
Figure 1-6 • MX Routing Structure
Clock Networks
The 40MX devices have one global clock distribution
network (CLK). A signal can be put on the CLK network
by being routed through the CLKBUF buffer.
In 42MX devices, there are two low-skew, high-fanout
clock distribution networks, referred to as CLKA and
CLKB. Each network has a clock module (CLKMOD) that
can select the source of the clock signal from any of the
following
The clock modules are located in the top row of I/O
modules. Clock drivers and a dedicated horizontal clock
track are located in each horizontal routing channel.
Clock input pads in both 40MX and 42MX devices can
also be used as normal I/Os, bypassing the clock
networks.
The A42MX36 device has four additional register control
resources, called quadrant clock networks
page
fanout resource to the contiguous logic modules within
its quadrant of the device. Quadrant clock signals can
originate from specific I/O pins or from the internal array
and can be used as a secondary register clock, register
clear, or output enable.
• Externally from the CLKA pad, using CLKBUF
• Externally from the CLKB pad, using CLKBUF
• Internally from the CLKINTA input, using CLKINT
• Internally from the CLKINTB input, using CLKINT
1-5). Each quadrant clock provides a local, high-
buffer
buffer
buffer
buffer
Segmented
Horizontal
Routing
(Figure 1-7 on page
Vertical Routing Tracks
1-5):
Antifuses
Logic
Modules
(Figure 1-8 on