A42MX24-PQ208 MICROSEMI, A42MX24-PQ208 Datasheet - Page 49

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A42MX24-PQ208

Manufacturer Part Number
A42MX24-PQ208
Description
Manufacturer
MICROSEMI
Datasheet

Specifications of A42MX24-PQ208

Family Name
42MX
Number Of Usable Gates
36000
Number Of Logic Blocks/elements
912
# Registers
1410
# I/os (max)
176
Process Technology
0.45um (CMOS)
Operating Supply Voltage (typ)
3.3/5V
Logic Cells
912
Device System Gates
36000
Propagation Delay Time
2.5/1.8ns
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant

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Table 30 •
Parameter Description
Input Module Predicted Routing Delays
t
t
t
t
t
Global Clock Network
t
t
t
t
t
t
f
TTL Output Module Timing
t
t
t
t
t
t
d
d
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to check the hold
4. Delays based on 35 pF loading.
IRD1
IRD2
IRD3
IRD4
IRD8
CKH
CKL
PWH
PWL
CKSW
P
MAX
DLH
DHL
ENZH
ENZL
ENHZ
ENLZ
TLH
THL
device performance. Post-route timing analysis or simulation is required to determine actual performance.
time for this macro.
A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, V
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Input Low to HIGH
Input High to LOW
Minimum
Width HIGH
Minimum
Width LOW
Maximum Skew
Minimum Period
Maximum
Frequency
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
Delta LOW to HIGH
Delta HIGH to LOW
Pulse
Pulse
4
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
1
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
‘–3’ Speed
2.2
2.4
2.2
2.4
4.7
4.8
CC
0.03
0.02
188
181
2.1
2.6
3.1
3.6
5.7
4.6
4.6
4.8
4.8
0.4
0.5
3.3
4.0
3.7
4.7
7.9
5.9
= 4.75V, T
v6.1
‘–2’ Speed
2.6
2.7
2.6
2.7
5.4
5.6
J
= 70°C)
0.02
0.03
175
168
4.6
5.4
6.8
2.4
3.0
3.6
4.2
6.6
5.3
5.3
5.6
5.6
0.5
0.6
3.8
4.3
9.1
3.01
‘–1’ Speed
2.9
3.1
2.9
6.1
6.3
10.4
0.03
0.03
160
154
2.2
3.4
4.1
4.8
7.5
6.0
6.0
6.3
6.3
0.5
0.7
4.3
5.2
4.9
6.1
7.7
‘Std’ Speed
3.4
3.6
3.4
3.6
7.2
7.5
40MX and 42MX FPGA Families
12.2
0.03
0.04
139
134
3.2
4.0
4.8
5.6
8.8
7.0
7.0
7.4
7.4
0.6
0.8
5.1
6.1
5.8
7.2
9.0
10.0
10.4
‘–F’ Speed
4.8
5.1
4.8
5.1
7.2
8.6
8.0
10.1
17.1
12.6
0.04
0.06
12.4
10.4
10.4
4.5
5.6
6.7
7.8
9.8
9.8
0.8
1.2
83
80
Units
ns/pF
ns/pF
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1-43

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