71V3556S200PF8 IDT, Integrated Device Technology Inc, 71V3556S200PF8 Datasheet - Page 16

71V3556S200PF8

Manufacturer Part Number
71V3556S200PF8
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of 71V3556S200PF8

Density
4.5Mb
Access Time (max)
3.2ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
200MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
17b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
400mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
36b
Number Of Words
128K
Lead Free Status / Rohs Status
Not Compliant
NOTES:
1. t
2. Measured as HIGH above 0.6V
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that t
6. Commercial temperature range only.
Output Parameters
Set Up Times
Hold Times
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CYC
F
CH
CL
CD
CDC
CLZ
CHZ
OE
OLZ
OHZ
SE
SA
SD
SW
SADV
SC
SB
HE
HA
HD
HW
HADV
HC
HB
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT
(1)
(2)
The specs as shown do not imply bus contention because t
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
(2)
F
Symbol
(3,4,5)
(3,4)
(3,4,5)
(3,4)
= 1/t
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
CYC
.
Clock Cycle Time
Clock Frequence
Clock High Pulse Width
Clock Low Pulse Width
Clock High to Valid Data
Clock High to Data Change
Clock High to Output Active
Clo ck High to Data High-Z
Output Enable Access Time
Output Enable Low to Data Active
Output Enable High to Data High-Z
Clock Enable Setup Time
Data In Setup Time
Read/Write (R/W) Setup Time
Chip Enable/Select Setup Time
Byte Write Enable (BWx) Setup Time
Clock Enable Hold Time
Data In Hold Time
Read/Write (R/W) Hold Time
Chip Enable/Select Hold Time
Byte Write Enable (BWx) Hold Time
Address Setup Time
Advance/Load (ADV/LD) Setup Time
Address Hold Time
Advance/Load (ADV/LD) Hold Time
Parameter
DDQ
and LOW below 0.4V
DDQ
CLZ
.
Min.
is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than t
0.5
0.5
0.5
0.5
0.5
0.5
0.5
____
1.8
1.8
____
____
____
1.5
1.5
1.5
1.5
1.5
1.5
1.5
5
0
1
1
1
CHZ
200MHz
(device turn-off) is about 1ns faster than t
(6)
Max.
200
____
____
____
3.2
____
____
3.2
____
3.5
____
____
____
____
____
____
____
____
____
____
____
____
____
____
6.42
3
16
Min.
____
1.8
1.8
____
____
____
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
6
0
1
1
1
166MHz
Max.
166
3.5
3.5
3.5
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
3
Commercial and Industrial Temperature Ranges
CLZ
Min.
7.5
____
2.2
2.2
____
____
____
1.7
1.7
1.7
1.7
1.7
1.7
1.7
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0
1
1
1
(device turn-on) at a given temperature and voltage.
133MHz
Max.
133
____
____
____
4.2
____
____
4.2
____
4.2
____
____
____
____
____
____
____
____
____
____
____
____
____
____
3
Min.
3.2
3.2
2.0
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
0.5
____
____
____
____
10
0
1
1
1
100MHz
Max.
100
____
____
____
____
____
3.3
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
5
5
5
5281 tbl 24
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CHZ
,

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