MC10EP05DT ON Semiconductor, MC10EP05DT Datasheet

Gates (AND / NAND / OR / NOR) 3.3V/5V ECL 2-Input

MC10EP05DT

Manufacturer Part Number
MC10EP05DT
Description
Gates (AND / NAND / OR / NOR) 3.3V/5V ECL 2-Input
Manufacturer
ON Semiconductor
Datasheet

Specifications of MC10EP05DT

Product
MUX Gates
Logic Family
ECL
Number Of Gates
1
Number Of Lines (input / Output)
4 / 2
High Level Output Current
- 50 mA
Low Level Output Current
50 mA
Propagation Delay Time
0.27 ns
Supply Voltage (max)
+/- 5.5 V
Supply Voltage (min)
+/- 3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-8
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
No RoHS Version Available

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MC10EP05, MC100EP05
3.3V / 5V ECL 2-Input
Differential AND/NAND
Description
The device is functionally equivalent to the EL05 and LVEL05
devices. With AC performance much faster than the LVEL05 device,
the EP05 is ideal for applications requiring the fastest
AC performance available.
Features
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 9
The MC10/100EP05 is a 2−input differential AND/NAND gate.
The 100 Series contains temperature compensation.
with V
with V
220 ps Typical Propagation Delay
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: V
NECL Mode Operating Range: V
Open Input Default State
Safety Clamp on Inputs
Q Output Will Default LOW with Inputs Open or at V
Pb−Free Packages are Available
EE
EE
= −3.0 V to −5.5 V
= 0 V
CC
CC
= 3.0 V to 5.5 V
= 0 V
EE
1
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
CASE 506AA
MN SUFFIX
CASE 948R
DT SUFFIX
CASE 751
D SUFFIX
H
K
5I
2X
D
TSSOP−8
*For additional marking information, refer to
8
(Note: Microdot may be in either location)
SOIC−8
Application Note AND8002/D.
DFN8
8
= MC10
= MC100
= MC10
= MC100
= Date Code
1
ORDERING INFORMATION
1
http://onsemi.com
8
1
8
1
MARKING DIAGRAMS*
ALYWG
HP05
Publication Order Number:
A
L
Y
W
G
ALYWG
HEP05
1
G
G
4
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
8
1
MC10EP05/D
8
1
ALYWG
KEP05
ALYWG
1
KP05
G
G
4

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MC10EP05DT Summary of contents

Page 1

MC10EP05, MC100EP05 3.3V / 5V ECL 2-Input Differential AND/NAND Description The MC10/100EP05 is a 2−input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ...

Page 2

Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Table 3. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of ...

Page 3

Table 4. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input Voltage I NECL Mode Input Voltage I Output Current out T Operating Temperature Range A T Storage Temperature ...

Page 4

Table 6. 10EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 5

Table 8. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note 13 Output LOW Voltage (Note 13 Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 6

Table 10. 100EP DC CHARACTERISTICS, NECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note 19 Output LOW Voltage (Note 19 Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 7

V 650 550 450 350 (JITTER) É É É É É É É É É É É É É É 250 É É É É É É É É É É É É É É 1.0 1.5 ...

Page 8

... ORDERING INFORMATION Device MC10EP05D MC10EP05DG MC10EP05DR2 MC10EP05DR2G MC10EP05DT MC10EP05DTG MC10EP05DTR2 MC10EP05DTR2G MC10EP05MNR4 MC10EP05MNR4G MC100EP05D MC100EP05DG MC100EP05DR2 MC100EP05DR2G MC100EP05DT MC100EP05DTG MC100EP05DTR2 MC100EP05DTR2G MC100EP05MNR4 MC100EP05MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D ...

Page 9

... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...

Page 10

K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) D −T− G SEATING PLANE PACKAGE DIMENSIONS TSSOP−8 ...

Page 11

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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