CS5522-AS Cirrus Logic Inc, CS5522-AS Datasheet - Page 38

• Manufacturer Part Number: CS5522-AS
• Description: ADC (A/D Converters) 2-Ch 24-Bit Delta Sigma ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5522-AS

• Architecture: Delta-Sigma
• Conversion Rate: 0.617 KSPs
• Input Type: Voltage
• Maximum Power Dissipation: 500 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: No

SCLKs for each Setup referenced are required to
read the conversion words from the data FIFO. The
first 8 SCLKs are used to clear the SDO flag. Ev-
ery 24 bits thereafter consist of the data words of
each Setup that was referenced, until all of the data
has been read from the part. If, during the first 8
SCLKs, "0000 0000" is provided on SDI, the con-
verter will remain in this conversion mode, and be-
gin performing the next set of conversions. To exit
this conversion mode, "1111 1111" must be pro-
vided on SDI during the first 8 SCLKs. If the user
decides to exit, 24 more SCLKs for each referenced
Setup are required to read the final conversion data
set from the FIFO and return to command mode.
1.4.2 Calibration Protocol
To perform a calibration, the user must send a com-
mand byte with its MSB=1, its pointer bits
(CSRP3-CSRP0) set to address the desired Setup to
be calibrated, and the appropriate calibration bits
(CC2-CC0) set to choose the type of calibration to
be performed. Proper calibration assumes that the
CSRs have been previously initialized because the
information concerning the physical channel, its
filter rate, gain range, and polarity, comes from the
channel-setup register being addressed by the
pointer bits in the command byte.
Once the CSRs are initialized, all future calibra-
tions can be performed with one command byte.
Once a calibration cycle is complete, SDO falls and
the results are stored in either the gain or offset reg-
ister for the physical channel being calibrated. Note
that if additional calibrations are performed on the
same physical channel referenced by a different
Setup with different filter rates, gain ranges, or con-
version modes, the last calibration results will re-
place the effects from the previous calibration as
only one offset and gain register is available per
physical channel. One final note is that only one
calibration is performed with each command byte.
To calibrate all the channels additional calibration
commands are necessary.
38
1.4.3 Example of Using the CSRs to Perform
Conversions and Calibrations
Any time a calibration command is issued (CB=1
and proper CC2-CC0 bits set) or any time a normal
conversion
CC2=CC1=CC0=0, MC=0), the bits D6-D3 (or
CSRP3 - CSRP0) in the command byte are used as
pointers to address one of the Setups in the chan-
nel-setup registers (CSRs). Five example situations
that a user might encounter when acquiring a con-
version or calibrating the converter follow. These
examples assume that the user is using a CS5528
(16 Setups) and that its CSRs are programmed with
the following physical channel order:
6, 1, 6, 2, 6, 3, 6, 4, 6, 5, 6, 2, 6, 7, 6, 8.
Example 1:
The configuration register has the following bits as
shown: DP3-DP0 = ‘XXXX’, MC = 0, L = 0,
RC = X. The command issued is ‘1111 0000’.
These settings instruct the converter to convert the
15th Setup once, as CPB3 - CPB0 = ‘1110’ (which
happens to be physical channel 6 in this example).
SDO falls after physical channel 6 is converted. To
read the conversion results, 32 SCLKs are then re-
quired. Once acquired, the serial port returns to the
command mode.
Example 2:
The configuration register has the following bits as
shown: DP3-DP0 = ‘XXXX’, MC = 0, LP = 1,
RC = 1. The command byte issued is ‘1001 1000’.
These settings instruct the converter to repeatedly
convert the fourth Setup as CPB3-CPB0 = ‘0011’
(which happens to be physical channel 2 in this ex-
ample). SDO falls after physical channel 2 is con-
verted. To read the conversion results 32 SCLKs
are required. The first 8 SCLKs are needed to clear
the SD0 flag. If ‘0000 0000’ is provided to the SDI
pin during the first 8 SCLKs, the conversion is per-
formed again on physical channel 2. The converter
will remain in data mode until ‘1111 1111’ is pro-
vided during the first 8 SCLKs following the fall of
command
CS5521/22/23/24/28
is
issued
DS317F8
(CB=1,