CS5522-ASZ Cirrus Logic Inc, CS5522-ASZ Datasheet
CS5522-ASZ
Specifications of CS5522-ASZ
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CS5522-ASZ Summary of contents
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... General Description The CS5521/22/23/24/28 are highly integrated ∆Σ ana- log-to-digital converters (ADCs) which use charge- balance techniques to achieve 16-bit (CS5521/23) and 24-bit (CS5522/24/28) performance. The ADCs come as either (CS5523/24), or eight-channel (CS5528) devices and include a low-input-current, chopper-stabilized instru- mentation amplifier. To permit selectable input spans of 25 mV, 55 mV, 100 mV ...
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... TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5 ANALOG CHARACTERISTICS ................................................................................................ 5 TYPICAL RMS NOISE, CS5521/23.......................................................................................... 7 TYPICAL NOISE FREE RESOLUTION (BITS), CS5521/23 .................................................... 7 TYPICAL RMS NOISE, CS5522/24/28..................................................................................... 8 TYPICAL NOISE FREE RESOLUTION (BITS), CS5522/24/28 ............................................... DIGITAL CHARACTERISTICS........................................................................................... DIGITAL CHARACTERISTICS........................................................................................... 9 DYNAMIC CHARACTERISTICS ............................................................................................ 10 RECOMMENDED OPERATING CONDITIONS ..................................................................... 10 ABSOLUTE MAXIMUM RATINGS ......................................................................................... 10 SWITCHING CHARACTERISTICS ........................................................................................ 11 2 ...
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Unipolar/Bipolar Bit ............................................................................. 28 2.2.8 Configuration Register ........................................................................................ 28 2.2.8.1 Chop Frequency Select ...................................................................... 28 2.2.8.2 Conversion/Calibration Control Bits .................................................... 28 2.2.8.3 Power Consumption Control Bits ........................................................ 28 2.2.8.4 Charge Pump Disable ......................................................................... 29 2.2.8.5 Reset System Control Bits ...
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... Figure 18. Filter Response (Normalized to Output Word Rate = 1) .............................................. 42 Figure 19. Typical Linearity Error for CS5521/23 .......................................................................... 42 Figure 20. Typical Linearity Error for CS5522/24/28 ..................................................................... 42 Figure 21. CS5522 Configured to use on-chip charge pump to supply NBV ................................ 43 Figure 22. CS5522 Configured for ground-referenced Unipolar Signals....................................... 44 Figure 23. CS5522 Configured for Single Supply Bridge Measurement ....................................... 44 Figure 24 ...
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... 400 NBV (Note 6) - 6.0 N/A N/A - 1.2 - 500 - 120 - 110 : for the CS5521/23 and for the CS5522/24/28 CS5521/22/23/24/28 CS5522/24/28 Min Typ Max ±0.0007 ±0.0015 - ±16 ±2 - ±32 ±4 ±32 ± ±31 ±8 ±31 - ±62 ±16 ± ...
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ANALOG CHARACTERISTICS Parameter Analog Input Common Mode + Signal on AIN+ or AIN- NBV = -1.8 to -2.5 V Range = 25 mV, 55 mV, or 100 mV Range = NBV = AGND ...
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TYPICAL RMS NOISE, CS5521/23 Output Rate -3 dB Filter (Sps) Frequency 1.88 1.64 3.76 3.27 7.51 6.55 15.0 12.7 30.0 25.4 61.6 (Note 12) 50.4 84.5 (Note 12) 70.7 101.1 (Note 12) 84.6 Notes: 10. Wideband noise aliased into the ...
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... Resolution is LOG((Input Range)/(6.6xRMS Noise))/LOG(2) rounded to the nearest bit. Also, the CS5522/24/28’s output conversions are 24 bits. Noise free Resolution numbers are based upon VREF = 2.5 V and XIN = 32.768 kHz. The values will be affected directly by changes in VREF, but the effects due to changes in the XIN frequency will be minor ...
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V DIGITAL CHARACTERISTICS See Notes 2 and 18.)) Parameter High-level Input Voltage All Pins Except XIN and SCLK Low-level Input Voltage All Pins Except XIN and SCLK High-level Output Voltage All Pins Except CPD and SDO (Note 19) Low-level ...
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DYNAMIC CHARACTERISTICS Parameter Modulator Sampling Frequency Filter Settling Time to 1/2 LSB (Full-scale Step) RECOMMENDED OPERATING CONDITIONS Parameter DC Power Supplies Analog Reference Voltage Negative Bias Voltage Notes: 20. All voltages with respect to ground. ABSOLUTE MAXIMUM RATINGS Parameter DC ...
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... CS Rising to SDO Hi-Z Notes: 25. Device parameters are specified with a 32.768 kHz clock; however, clocks up to 200 kHz (CS5522/24/28) or 130 kHz (CS5521/23) can be used for increased throughput. 26. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 27. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source ...
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Figure 1. Continuous Running SCLK Timing (Not to Scale ...
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... Sps, 7.51 Sps, 15 Sps, 30 Sps, 61.6 Sps, 84.5 Sps, and 101.1 Sps (XIN = 32.768 kHz). The devices are capable of producing output update rates up to 617 Sps when a 200 kHz clock is used (CS5522/24/28 401 Sps using a 130 kHz clock (CS5521/23). Further note that the digital fil- CS5522 AIN2+ ...
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Instrumentation Amplifier The instrumentation amplifier is chopper stabilized and is activated any time conversions are performed with the low-level input ranges, ≤100 mV. The am- plifier is powered from VA+ and from the NBV (Negative Bias Voltage) pin CS5521/22/23/24/28 ...
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Analog Input Span Considerations The CS5521/22/23/24/28 is designed to measure full-scale ranges of 25 mV, 55 mV, 100 mV 2.5 V, and 5 V. Other full scale values can be ac- commodated by performing a system calibration ...
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Figure 7 illustrates an example circuit. Re- fer to Application Note 158 for more details on high-voltage ...
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A group of registers, called Channel Set-up Regis- ters, are also included in the converters. These reg- isters are used to hold pre-loaded conversion instructions. Each channel set-up ...
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System Initialization When power to the CS5521/22/23/24/28 is applied, the chips are held in a reset condition until the 32.768 kHz oscillator has started and a counter- timer elapses. Due to the high Q of the 32.768 kHz crystal, ...
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Command Register Quick Reference D7(MSB CS2 CS1 BIT NAME D7 Command Bit, CB D6-D4 Channel Select Bits, CSB2-CSB0 D3 Read/Write, R/W D2-D0 Register Select Bit, RSB2-RSB0 D7(MSB CSRP3 CSRP2 CSRP1 BIT NAME D7 ...
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Command Register Descriptions READ/WRITE INDIVIDUAL OFFSET CALIBRATION REGISTER D7(MSB CS2 : Function These commands are used to access each offset register separately. CS1 - CS0 decode the registers accessed. R/W (Read/Write) 0 Write to selected register. 1 ...
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READ/WRITE CONFIGURATION REGISTER D7(MSB Function: These commands are used to read from or write to the configuration register. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. READ/WRITE CHANNEL-SETUP REGISTER(S) D7(MSB ...
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PERFORM CONVERSION D7(MSB CSRP3 CSRP2 Function: These commands instruct the ADC to perform conversions on the physical input channel point the pointer bits (CSRP2 - CSRP0) in the channel-setup registers. The particular type of conversion ...
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PERFORM CALIBRATION D7(MSB CSRP3 CSRP2 Function: These commands instruct the ADC to perform a calibration on the physical input channel refer- enced which is chosen by the command byte pointer bits (CSRP3 - CRSP0). CSRP [3:0] (Channel Setup ...
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SYNC1 D7(MSB Function: Part of the serial port re-initialization sequence. SYNC0 D7(MSB Function: End of the serial port re-initialization sequence. NULL D7(MSB Function: This command is used to clear a port ...
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Serial Port Interface The CS5521/22/23/24/28’s serial interface consists of four control lines: CS, SCLK, SDI, SDO. Figure 10 illustrates the serial sequence necessary to write to, or read from the serial port’s registers. CS (Chip Select) is the control ...
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Reading/Writing the Offset, Gain, and Configuration Registers The CS5521/22/23/24/28’s offset, gain, and config- uration registers are accessed individually and can be read from or written to. To write to an offset, a gain, or the configuration register, the user ...
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CSR (Channel-Setup Register) #1 Setup 1 Setup 2 Bits <47:36> Bits <35:24> #2 Setup 3 Setup 4 Bits <23:12> Bits <11:0> CS5521/22 D23(MSB) D22 D21 D20 A1 A0 CS2 CS1 D11 D10 CS2 CS1 BIT NAME D23-D22/ ...
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... Power Consumption Control Bits The CS5522/24/28 devices accommodate four power consumption modes: normal, low power, standby, and sleep. The CS5521/23 accommodate three power consumption modes: normal, standby, and sleep ...
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... CS5522/24/28 typically consume 9.0 mW. The CS5521/23 typically consume 6.0 mW. The low- power mode is an alternate mode in the CS5522/24/28 that reduces the consumed power to 5.5 mW entered by setting bit D8 (the low- power mode bit) in the configuration register to logic 1. Slightly degraded noise or linearity perfor- mance should be expected in the low-power mode ...
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... Setups are converted when MC=1 and a command byte 1111 with its MSB = 1 is issued. Note that the CS5522 has two CSRS, the CS5524 has four CSRs, and the CS5528 has 8 CSRs Standby Mode (Oscillator active, allows quick power-up). ...
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Calibration The CS5521/22/23/24/28 offer four different cali- bration functions including self calibration and sys- tem calibration. However, after the devices are reset, the converter is functional and can perform measurements without being calibrated. In this case, the converter will ...
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AIN- pin must be at the proper com- mon-mode voltage as specified in ‘Common Mode +Signal AIN+/-’ specification in the Analog Input section (if AIN- = ...
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In either case, the calibration signals must be within the specified calibration limits for each specific calibration step (refer to the ‘System Calibration Specifications’ in ANALOG CHARACTERISTICS system gain calibration is performed the ...
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The variables are defined below First calibration voltage V1 = Second calibration voltage (greater than V0 Result of any uncalibrated conversion Ru0 = Result of uncalibrated conversion V0 (24-bit integer or 2’s complement) Ru1 = Result ...
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Further note that the type of conversion(s) performed and the way to access the resulting data from the FIFO is determined by the MC (multiple conversion), the LP (loop), the RC (read convert), and the DP (depth ...
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SDO line. If, during the first 8 SCLKs, "00000000" is provided on SDI, the converter will remain in this conversion mode, and continue to perform conversions on the selected Setup. To exit this conversion mode, "11111111" must be provid- ed ...
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Repeated Multiple-Setup Conversions without Wait ( this conversion mode, the ADC will repeatedly perform conversions, referencing multiple Setups. The CSRP bits in the command word are ignored in this mode. ...
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SCLKs for each Setup referenced are required to read the conversion words from the data FIFO. The first 8 SCLKs are used to clear the SDO flag. Ev- ery 24 bits thereafter consist of the data words of each Setup ...
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SD0. After ‘1111 1111’ is provided, 24 additional SCLKs are required to transfer the last 3 bytes of conversion data before the serial port will return to the command mode. Example 3: The configuration register has the following bits as ...
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... Note: VFS in the table equals the voltage between ground and full scale for any of the unipolar gain ranges, or the voltage between ± full scale for any of the bipolar gain ranges. See text about error flags under overrange conditions. Table 6. Output Coding for 16-bit CS5521/23 and 24-bit CS5522/24/28 40 the conversions MSB first. The last byte of the con- version data word (CS5521/23 only) contains data monitoring flags ...
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... Conversion Data Bits [23:8 for CS5521/23; 23:0 for CS5522/24/28] These bits depict the latest output conversion. OD (Oscillation detect Flag Bit) 0 Bit is clear when oscillatory condition in modulator does not exist (bit is read only). 1 Bit is set any time an oscillatory condition is detected in the modulator. This does not occur under normal operation conditions, but may occur when the input is extremely overranged ...
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... Figure 18. Filter Response (Normalized to Output Word Rate = 15 Sps) 42 The converters will operate with an external (CMOS compatible) clock with frequencies up to 130 kHz (CS5521/23) or 200 kHz (CS5522/24/28). Figures 19 and 20 detail the CS5521/23 and CS5522/24/28’s performance (respectively) at in- creased clock rates. The 32.768 kHz crystal is normally specified as a ...
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... rre Ω Figure 21. CS5522 Configured to use on-chip charge pump to supply NBV DS317F4 on the converter. For the 25 mV, 55 mV, and 100 mV ranges, the signals being digitized must have a common mode between +1.85 to +2.65 V (NBV = 0 V). Although CS5521/22/23/24/28 are optimized for the measurement of thermocouple outputs, they are also well suited for the measurement of ratiometric bridge transducer outputs ...
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... Figure 22. CS5522 Configured for ground-referenced Unipolar Signals + alo Figure 23. CS5522 Configured for Single Supply Bridge Measurement Ω µ S5522 Ω 0.1 µ S5522 CS5521/22/23/24/ µ ptio rce ria ata In te rfa 0.1 µ 32. 0kH tio urce ria l D ata 8 Inte rfa ce ...
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... When a larger pumping capaci- tor is used, the charge pump can source more current to power external loads. Refer to Applications Note 152 “Using the CS5521/23, CS5522/24/28, and CS5525/26 Charge Pump Drive for External Loads” for more details on using the charge pump with exter- nal loads ...
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The converter input ranges are specified with a voltage reference of 2.5 V. The device can be op- erated ...
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Note that while the RS bit is set to ‘1’ all other register bits in the ADC will be reset to their default state, and the RS bit must be set to ‘0’ for normal operation of the ...
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... LOGIC OUTPUT CHARGE PUMP DRIVE SERIAL DATA INPUT CHIP SELECT CRYSTAL IN 48 AGND VREF+ VOLTAGE REFERENCE INPUT 20 1 CS5521 VA+ VREF- VOLTAGE REFERENCE INPUT 2 19 CS5522 AIN1+ AIN2+ DIFFERENTIAL ANALOG INPUT 3 18 AIN1- AIN2- DIFFERENTIAL ANALOG INPUT 4 17 NBV A1 LOGIC OUTPUT SCLK ...
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... Measurement and Reference Inputs AIN1+, AIN1-, AIN2+, AIN2- AIN3+, AIN3-, AIN4+, AIN4- - Differential Analog Input. Differential input pins into the CS5522 and CS5524 devices. AIN1+, AIN2+, AIN3+, AIN4+, AIN5+, AIN6+, AIN7+, AIN8+ - Single-Ended Analog Input. Single-ended input pins into the CS5528. ...
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NBV - Negative Bias Voltage. Input pin to supply the negative supply voltage for the 20X gain instrumentation amplifier and coarse/fine charge buffers. May be tied to AGND if AIN+ and AIN- inputs are centered around +2 ...
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SPECIFICATION DEFINITIONS Linearity Error The deviation of a code from a straight line which connects the two endpoints of the A/D Converter transfer function. One endpoint is located 1/2 LSB below the first code transition and the other endpoint ...
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... Plastic SSOP CS5521-ASZ 20-pin 0.2" Plastic SSOP (Lead Free) CS5522-AP 20-pin 0.3" Plastic DIP CS5522-AS 20-pin 0.2" Plastic SSOP CS5522-ASZ 20-pin 0.2" Plastic SSOP (Lead Free) CS5523-AS 24-pin 0.2" Plastic SSOP CS5523-ASZ 24-pin 0.2" Plastic SSOP (Lead Free) CS5524-AP 24-pin 0.3" ...
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PACKAGE DIMENSION DRAWINGS 20 PIN PLASTIC (PDIP) (300 MIL) PACKAGE DRAWING E1 1 TOP VIEW DIM MIN A 0.000 A1 0.015 A2 0.115 b 0.014 b1 0.045 c 0.008 D 0.980 E 0.300 E1 0.240 e 0.090 eA 0.280 ...
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PIN SKINNY PLASTIC (PDIP) (300 MIL) PACKAGE DRAWING E1 1 TOP VIEW DIM MIN A 0.000 A1 0.015 A2 0.115 b 0.014 b1 0.045 c 0.008 D 1.230 E 0.300 E1 0.240 e 0.090 eA 0.280 eB 0.300 eC ...
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SSOP PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.002 A2 0.064 b 0.009 D 0.272 E 0.291 E1 0.197 e 0.022 L 0.025 ∝ 0° Notes: 1. “D” and “E1” are ...
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SSOP PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.002 A2 0.064 b 0.009 D 0.311 E 0.291 E1 0.197 e 0.022 L 0.025 ∝ 0° Notes: 1. “D” and “E1” are ...