CS5522-ASZ Cirrus Logic Inc, CS5522-ASZ Datasheet - Page 21

IC ADC 24BIT SIG/DELT 20-SSOP

CS5522-ASZ

Manufacturer Part Number
CS5522-ASZ
Description
IC ADC 24BIT SIG/DELT 20-SSOP
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CS5522-ASZ

Number Of Converters
1
Package / Case
20-SSOP
Number Of Bits
24
Data Interface
Serial
Power Dissipation (max)
14.8mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Number Of Adc Inputs
1
Architecture
Delta-Sigma
Conversion Rate
617 SPs
Resolution
24 bit
Input Type
Voltage
Interface Type
Serial (3-Wire)
Voltage Reference
2.5 V
Supply Voltage (max)
5 V
Supply Voltage (min)
25 mV
Maximum Power Dissipation
500 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Input Voltage
25 mV to 5 V
Minimum Operating Temperature
- 40 C
Package
20SSOP
Sampling Rate
0.617 KSPS
Number Of Adcs
1
Number Of Analog Inputs
2
Digital Interface Type
Serial (3-Wire, SPI, Microwire)
Polarity Of Input Voltage
Unipolar|Bipolar
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
598-1104-5

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READ/WRITE CONFIGURATION REGISTER
READ/WRITE CHANNEL-SETUP REGISTER(S)
DS317F4
D7(MSB)
D7(MSB)
Function:
R/W (Read/Write)
Function
R/W (Read/Write)
0
0
0
1
0
1
:
D6
D6
These commands are used to read from or write to the configuration register.
Write to selected register.
Read from selected register.
These commands are used to access the channel-setup registers (CSRs). The number of
CSRs accessed is determined by the device being used and the number of CSRs that are being
accessed (i.e. the depth bits in the configuration register determine the number of levels ac-
cessed). This register is 48-bits long (4 Setups) for the CS5521/22, 96-bits long (8 Setups) for
the CS5523/24, and 192-bits (16 Setups) long for the CS5528.
Write to selected register.
Read from selected register.
0
0
D5
D5
0
0
D4
D4
0
0
R/W
R/W
D3
D3
D2
D2
0
1
CS5521/22/23/24/28
D1
D1
1
0
D0
D0
1
1
21

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