H57V2562GTR-75C HYNIX SEMICONDUCTOR, H57V2562GTR-75C Datasheet - Page 6

• Manufacturer Part Number: H57V2562GTR-75C
• Description: 58T1903
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H57V2562GTR-75C

• Memory Type: SDRAM
• Memory Configuration: 16M X 16
• Access Time: 6ns
• Interface Type: LVTTL
• Memory Case Style: TSOPII
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Memory Size: 256 Mbit
• Rohs Compliant: Yes

Rev 1.0 / Dec. 2010
54_TSOPII Pin DESCRIPTIONS
RAS, CAS, WE
LDQM, UDQM
DQ0 ~ DQ15
V
V
DDQ
SYMBOL
A0 ~ A12
BA0, BA1
DD
CKE
CLK
NC
CS
/ V
/ V
SS
SSQ
SUPPLY
SUPPLY
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
TYPE
I/O
I/O
-
Clock :
The system clock input. All other inputs are registered to the SDRAM on the rising edge
of CLK
Clock Enable:
Controls internal clock signal and when deactivated, the SDRAM will be one of the states
among power down, suspend or self refresh
Chip Select:
Enables or disables all inputs except CLK, CKE and DQM
Bank Address:
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address: RA0 ~ RA12, Column Address: CA0 ~ CA8
Auto-precharge flag: A10
Command Inputs:
RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask:
Controls output buffers in read mode and masks input data in write mode
Data Input / Output:
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection : These pads should be left unconnected
DESCRIPTION
Synchronous DRAM Memory 256Mbit
H57V2562GTR Series
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