CY7C43642AV-10AC Cypress Semiconductor Corp, CY7C43642AV-10AC Datasheet - Page 19

• Manufacturer Part Number: CY7C43642AV-10AC
• Description: FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 x 2 120-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C43642AV-10AC

• Package: 120TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 72 Kb
• Organization: 1Kx36x2
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

Document #: 38-06020 Rev. *C
Switching Waveforms
Note:
35. t
EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard mode)
CLKB
CSB
MBB
ENB
B
CLKA
CSA
W/RA
ENA
A
W/RB
FFB/IRB
EFA/OFA
MBA
rising CLKB edge and rising CLKA edge is less than t
SKEW1
0–35
0–35
is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the
LOW
LOW
HIGH
LOW
LOW
LOW
FIFO2 Empty
(continued)
t
t
t
ENS
ENS
DS
W1
t
t
ENH
t
ENH
DH
t
SKEW1
[35]
t
SKEW1
CLKH
t
CLK
, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
t
CLKL
t
REF
t
CLKH
t
CLK
t
ENS
t
CLKL
t
ENH
t
t
REF
A
W1
CY7C43642AV
CY7C43662AV
CY7C43682AV
Page 19 of 30