CY7C43642AV-10AC Cypress Semiconductor Corp, CY7C43642AV-10AC Datasheet - Page 21

• Manufacturer Part Number: CY7C43642AV-10AC
• Description: FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 x 2 120-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C43642AV-10AC

• Package: 120TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 72 Kb
• Organization: 1Kx36x2
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

Document #: 38-06020 Rev. *C
Switching Waveforms
Note:
37. t
FFA Flag Timing and First Available Write when FIFO1 is Full (CY Standard mode)
CLKB
CSB
W/RB
MBB
ENB
B
CLKA
FFA/IRA
CSA
W/RA
MBA
ENA
A
EFB/ORB
rising CLKB edge and rising CLKA edge is less than t
0–35
0 35
SKEW1
is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the
Previous Word in FIFO1
Output Register
LOW
LOW
HIGH
HIGH
HIGH
LOW
FIFO1 Full
t
CLKH
t
CLK
t
CLKL
t
(continued)
ENS
t
ENH
t
SKEW1
t
A
[37]
Next Word From FIFO1
t
CLKH
SKEW1
t
CLK
, then the transition of FFA HIGH may occur one CLKA cycle later than shown.
t
CLKL
t
WFF
t
t
ENS
ENS
t
DS
t
t
ENH
t
ENH
DH
t
WFF
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