MACH445-15YC Lattice, MACH445-15YC Datasheet - Page 16

• Manufacturer Part Number: MACH445-15YC
• Description: CPLD MACH 4 Family 128 Macro Cells 47.6MHz EECMOS Technology 5V 100-Pin PQFP Tray
• Manufacturer: Lattice

Specifications of MACH445-15YC

• Package: 100PQFP
• Family Name: MACH 4
• Number Of Macro Cells: 128
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 64
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 47.6 MHz
• Number Of Product Terms Per Macro: 20
• Memory Type: EEPROM
• Re-programmability Support: Yes
• Operating Temperature: 0 to 70 °C

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
(continued)
Notes:
1. See Switching Test Circuit at the end of this Data Book for test conditions.
2. Parameters measured with 32 outputs switching.
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
4. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
16
Input Register with Zero-Hold-Time Option
Parameter
Symbol
where frequency may be affected.
t
t
t
t
t
t
t
t
SLLA
SLLS
PDLL
PDL
SIR
HIR
SIL
HIL
Parameter Description
Input, I/O, or Feedback to Output Through
Transparent Input Latch
Input Register Setup Time
Input Register Hold Time
Input Latch Setup Time
Input Latch Hold Time
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Product Term Output
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Gate
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
MACH445-15/20 (Com’l)
Gate
Min
16
18
6
0
6
0
-15
Max
23
25
Min
20
24
8
0
8
0
-20
Max
30
32
Unit
ns
ns
ns
ns
ns
ns
ns
ns