MT9044AL Zarlink, MT9044AL Datasheet - Page 6

• Manufacturer Part Number: MT9044AL
• Description: Framer E1/OC3/T1 5V 44-Pin MQFP
• Manufacturer: Zarlink

Specifications of MT9044AL

• Package: 44MQFP
• Maximum Data Rate: 2.048 Mbps
• Number Of Transceivers: 1
• Standard Framing Format: E1|OC3|T1
• Maximum Supply Current: 90 mA
• Minimum Single Supply Voltage: 4.5 V
• Maximum Single Supply Voltage: 5.5 V

Pin Description (continued)
Functional Description
The MT9044 is a Multitrunk System Synchronizer, providing timing (clock) and synchronization (frame) signals to
interface circuits for T1 and E1 Primary Rate Digital Transmission links.
Figure 1 shows the functional block diagram which is described in the following sections.
Reference Select MUX Circuit
The MT9044 accepts two simultaneous reference input signals and operates on their falling edges. Either the
primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE
Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Tables
1, 4 and 5.
Frequency Select MUX Circuit
The MT9044 operates with one of three possible input reference frequencies (8 kHz, 1.544 MHz or 2.048 MHz).
The frequency select inputs (FS1 and FS2) determine which of the three frequencies may be used at the reference
inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST) must be
performed after every frequency select input change. Operation with FS1 and FS2 both at logic low is reserved and
must not be used. See Table 1.
PLCC
Pin #
37
38
39
40
41
42
43
44
MQFP
Pin #
31
32
33
34
35
36
37
38
Name
RSEL
TMS
MS1
RST
FS2
FS1
TDI
IC
Mode/Control Select 1 (TTL Input).
the rising edge of F8o. See pin description for MS2. This pin is internally pulled
down to VSS.
Reference Source Select (TTL Input). In Manual Control, a logic low selects the
PRI (primary) reference source as the input reference signal and a logic high
selects the SEC (secondary) input. In Automatic Control, this pin must be at logic
low. The logic level at this input is gated in by the rising edge of F8o. See Table 2.
This pin is internally pulled down to VSS.
Internal Connection. Tie low for normal operation.
Frequency Select 2 (TTL Input). This input, in conjunction with FS1, selects
which of three possible frequencies (8 kHz, 1.544 MHz, or 2.048 MHz) may be
input to the PRI and SEC inputs. See Table 1.
Frequency Select 1 (TTL Input). See pin description for FS2.
Test Serial Data In (TTL Input). JTAG serial test instructions and data are shifted
in on this pin. This pin is internally pulled up to V
Reset (Schmitt Input). A logic low at this input resets the MT9044. To ensure
proper operation, the device must be reset after changes to the method of control,
reference signal frequency changes and power-up. The RST pin should be held
low for a minimum of 300 ns. While the RST pin is low, all frame outputs except
RSP and TSP and all clock outputs except C6o, C16o and C19o are at logic high.
The RSP, TSP, C6o and C16o are at logic low during reset. The C19o is free-
running during reset. Following a reset, the input reference source and output
clocks and frame pulses are phase aligned as shown in Figure 19.
Test Mode Select (TTL Input). JTAG signal that controls the state transitions of
the TAP controller. This pin is internally pulled up to V
Zarlink Semiconductor Inc.
MT9044
6
Description
The logic level at this input is gated in by
DD
.
DD
.
Data Sheet