MT90869AG Zarlink, MT90869AG Datasheet
MT90869AG
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MT90869AG Summary of contents
Page 1
... Flexible 16 K Digital Switch (F16kDX) Ordering Information MT90869AG MT90869AG2 *Pb Free Tin/Silver/Copper *Note: the package thickness is different than the MT90869AG (see drawing at the end of the data sheet). • Local port accepts 32 ST-BUS streams with data rates of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or 16.384 Mb/s, in any combination • ...
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... Per stream subrate switching at 4 bit, 2 bit and 1 bit depending on stream data rate Applications • Central Office Switches (Class 5) • Mediation Switches • Class-independent switches • Access Concentrators • Scalable TDM-Based Architectures • Digital Loop Carriers MT90869 2 Zarlink Semiconductor Inc. Data Sheet ...
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... The microprocessor may monitor channel data in the backplane and local data memories. The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port. The MT90869 is manufactured body, 1.27 mm ball-pitch, 272-PBGA to JEDEC standard MS- 034 BAL-2 Iss. A. MT90869 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Bit Error Rate Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.0 Memory Built-In-Self-Test (BIST) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.1 Test Access Port (TAP 11.2 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.2.1 Test Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.2.2 Test Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.2.2.1 The Boundary-Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.2.2.2 The Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 MT90869 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Local Output Bit Rate Resisters (LOBRR0-31 13.13 Backplane Bit Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.13.1 Backplane Input Bit Rate Registers (BIBRR0-31 13.13.2 Backplane Output Bit Rate Registers (BOBRR0-31 13.14 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.15 Revision Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 MT90869 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 25 - GCI BUS Backplane Data Timing Diagram (32 Mb/s, 16 Mb/ Figure 26 - ST-BUS Local Timing Diagram (16 Mb/ Figure 27 - ST-BUS Local Data Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/ Figure 28 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 29 - Output Driver Enable (ODE Figure 30 - Motorola Non-Multiplexed Bus Timing MT90869 List of Figures 6 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 44 - Output Bit Rate (LOBR) Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 45 - Backplane Input Bit Rate Register (BIBRRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 46 - Backplane Input Bit Rate (BIBR) Programming Table Table 47 - Backplane Output Bit Rate Register (BOBRRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 48 - Backplane Output Bit Rate (BOBRR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 MT90869 List of Tables 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 49 - Memory BIST Register (MBISTR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 50 - Revision Control Register (RCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 MT90869 List of Tables 8 Zarlink Semiconductor Inc. Data Sheet ...
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... Changed description to specify Bit 6, C8IPOL must be set high for rising clock edge frame boundary alignment operation. Removed waveforms showing C8i falling edge frame boundary option. Removed waveforms showing C8i falling edge frame boundary option. 9 Zarlink Semiconductor Inc. Data Sheet Change Change ...
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... Changed C8i frame boundary active edge from falling to rising edge. Changed C8i frame boundary active edge from falling to rising edge. Changed FPo and C8o to FPi and C8i respectively and showing rising C8i frame boundary active edge. 10 Zarlink Semiconductor Inc. Data Sheet Change ...
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... GND GND GND D4 VDD GND VDD GND FP8i _IO _PLL C8o FP8o C8i C16o FP16o VDD_ NC NC VDD_ CORE CORE (as viewed through top of package) 11 Zarlink Semiconductor Inc. Data Sheet BCST LCST LST LST LST LCST IC LST LST LST BCST LCST LCST ...
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... Mb/s (with 128 channels per stream), 4.096 Mb/s (with 64 channels per stream), or 2.048 Mb/s (with 32 channels per stream). The data-rate is independently programmable for each input stream Mb/s Mode, these pins are unused and should be externally connected to a defined logic level. 12 Zarlink Semiconductor Inc. Data Sheet ...
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... BCSTo0 is the output enable for BSTo[0,4,8,12], BCSTo1 is the output enable for BSTo[1,5,9,13], BCSTo2 is the output enable for BSTo[2,6,10,14], BCSTo3 is the output enable for BSTo[3,7,11,15]. Refer to descriptions of the BORS and ODE pins for control of the output High or High-Impedance state. 13 Zarlink Semiconductor Inc. Data Sheet ...
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... LORS and BORS external control pins, respectively. It clears the device registers and internal counters. This pin must stay low for more than 2 cycles of input clock C8i for the reset to be invoked. 14 Zarlink Semiconductor Inc. Data Sheet ...
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... LCSTo0 is the output enable for LSTo[0,4,8,12,16,20,24,28], LCSTo1 is the output enable for LSTo[1,5,9,13,17,21,25,29], LCSTo2 is the output enable for LSTo[2,6,10,14,18,22,26,30], LCSTo3 is the output enable for LSTo[3,7,11,15,19,23,27,31]. Refer to descriptions of the LORS and ODE pins for control of the output High or High-Impedance state. 15 Zarlink Semiconductor Inc. Data Sheet ...
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... LCSTo0-3 driven low. Following initialization, the Local stream outputs may be set active or high impedance using the ODE pin per- channel basis with the LE bit in Local Connection Memory. No Connect No connection to be made. Internal Connects These inputs MUST be held LOW. 16 Zarlink Semiconductor Inc. Data Sheet ...
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... In this case, the MT90869 can be used as shown in Figure 4 to give the full 16,384 x 16,384 channel capacity. BSTi0-31 32 streams INPUT LSTi0-31 32 streams Figure 4 - 16,384 x 16,384 Channels (16 Mb/s), Unidirectional Switching MT90869 LSTo0-31 32 streams LSTi0-31 32 streams MT90869 BSTo0-31 32 streams LSTo0-31 32 streams MT90869 17 Zarlink Semiconductor Inc. Data Sheet LOCAL OUTPUT ...
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... BSTi0-31 LSTi0-15 BSTo0-31 LSTo0-15 Total 48 streams input and 48 output Figure Blocking Configuration MT90869 MT90869 Total 16 streams input and 16 streams output 18 Zarlink Semiconductor Inc. Data Sheet LSTi16-31 LSTo16-31 ...
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... Figure 6, Local Port Timing Diagram for 2,4,8 and 16 Mb/s stream rates. 2.2.1.1 Local Input Port The bit rate for each input stream is selected by writing to a dedicated Local Input Bit Rate Register (LIBRR0-31). Refer to Local Input Bit Rate Register (LIBRRn) Bits. MT90869 19 Zarlink Semiconductor Inc. Data Sheet ...
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... Mb/s - Non-32 Mb/s Mode Unused - 32 Mb/s Mode 2.048, 4.096, 8.192 or 16.384 Mb/s 2.048, 4.096, 8.192 or 16.384 Mb/s Channel Channel Channel Channel Channel Channel Channel 0 7 Channel Zarlink Semiconductor Inc. Data Sheet Channel 255 Channel 255 Channel 127 Channel 127 Channel Channel ...
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... High-impedance state controlled by the BE bit of the Backplane Connection Memory. The data source (i.e., from the Local or Backplane Data Memory) is determined by the BSRC bit of the Backplane Connection Memory. Refer to Section 6.2, Backplane Connection Memory and Section 12.4, Backplane Connection Memory Bit Definition. MT90869 21 Zarlink Semiconductor Inc. Data Sheet ...
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... Before the C8IPOL bit is set to one, the frame boundary will not be detected correctly. For the MT90869 Channel Channel Channel Channel Channel Channel Channel 0 6 Channel 0 1 Channel 0 7 Channel Zarlink Semiconductor Inc. Data Sheet Channel 510 Channel 511 Channel 510 Channel 511 Channel 255 Channel 255 Channel 127 Channel 127 ...
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... CH1 CH2 CH3 CH4 CH5 CH6 CH0 CH1 CH1 CH2 CH1 CH2 CH3 CH4 CH5 CH6 and 16 Mb/s 23 Zarlink Semiconductor Inc. Data Sheet CH2 CH3 CH4 CH5 CH7 CH8 CH9 CH10 CH11 CH2 CH3 CH4 CH5 CH7 CH8 CH9 CH10 CH11 ...
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... The local input delay is defined by the Local Input Delay registers, LIDR0 to LIDR31, corresponding to the local data streams, LSTi0 to LSTi31, and the backplane input delay is defined by the Backplane Input Delay registers, BIDR0 to BIDR31, which correspond to the backplane data streams, BSTi0 to BSTi31. MT90869 Channel Delay, 2 Ch0 Ch127 Zarlink Semiconductor Inc. Data Sheet Ch126 Ch127 Ch125 Ch126 Ch125 ...
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... Figure 10 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16 Mb/s MT90869 Ch0 Bit Delay, 1/4 Ch0 Bit Delay, 1/2 Ch0 Bit Delay, 3/4 Ch0 Bit Delay, 1 Ch0 Ch255 Ch255 Zarlink Semiconductor Inc. Data Sheet Ch1 Ch1 Ch1 Ch1 Ch1 Bit Delay, 7 1/2 Ch0 Bit Delay, 7 3/4 Ch0 ...
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... Mb/ Mb/s streams the advancement may cycles, -4 cycles or -6 cycles, which converts to MT90869 Ch0 Bit Delay, 1/4 Ch0 Bit Delay, 1/2 Ch0 Bit Delay, 3/4 Ch0 Bit Delay, 1 Ch0 Ch127 Ch127 Zarlink Semiconductor Inc. Data Sheet Ch1 Ch1 Ch1 Ch1 Ch1 Bit Delay, 7 1/2 Ch0 Bit Delay, 7 3/4 Ch0 ...
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... LCSTo1 outputs the channel control bits for streams LSTo1 13, 17, 21, 25 and 29. MT90869 Ch255 Bit 0 Bit 7 Bit Advancement, -2 Ch255 Bit 0 Bit 7 Bit Advancement, -4 Bit 0 Bit 7 Bit Advancement, -6 Bit 0 Bit 7 Bit 6 27 Zarlink Semiconductor Inc. Data Sheet Ch0 Bit 6 Bit 5 Ch0 Bit 6 Bit 5 Ch0 Bit 4 Bit 6 Bit 5 Ch0 Bit 5 Bit 4 ...
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... The LCSTo0-3 outputs remain active. Allocated Stream No. C16o LCSTo0 LCSTo1 LCSTo2 LCSTo3 1 Period 3-1 2039 0 1 3-3 2040 4 5 2041 8 9 2042 12 13 Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams MT90869 Channel No Mb/s Mb Zarlink Semiconductor Inc. Data Sheet 2 4 Mb ...
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... Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams MT90869 2 Channel No Mb/s 4 Mb/s 2 Mb etc etc etc etc etc etc etc etc etc Ch 254 Ch 127 254 Ch 127 255 Ch 127 255 Ch 127 255 Ch 127 255 Ch 127 255 Ch 127 Zarlink Semiconductor Inc. Data Sheet Frame Ch 0 Boundary etc etc ...
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... Note 2: The Channel Numbers presented relate to the data-rate selected for a specific stream. Note 3-1 to 3-4: See Section 4.1.1 for examples of Channel Control Bit for streams of different data-rates. MT90869 Channel No Mb/s Mb 255 Ch 127 255 Ch 127 255 Ch 127 etc etc etc etc 30 Zarlink Semiconductor Inc. Data Sheet 2 4 Mb Frame Boundary etc etc ...
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... MT90869 Channel 255 bits 7 Chan 0 Chan 0 Chan 127 Chan 127 Bit 5 Bit 4 Bit 3 Chan 0 Bit 6 Chan 63 Bit 1 One C16o period 31 Zarlink Semiconductor Inc. Data Sheet Chan 127 Chan 127 Chan 0 Bit 2 Bit 1 Bit 0 Bit 7 Chan 0 Chan 63 Bit 0 Bit 7 Chan 0 ...
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... Channel 1 will be transmitted during the C16o clock period nos. 9 and 17. Allocated Stream No. C16o BCSTo0 BCSTo1 1 Period 3-1 2039 0 1 3-3 2040 4 5 Table 3 - BCSTo Allocation of Channel Control Bits to the Output Streams (Non-32 Mb/s Mode) MT90869 Channel No. BCSTo2 BCSTo3 16 Mb Zarlink Semiconductor Inc. Data Sheet 2 4 Mb ...
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... Table 3 - BCSTo Allocation of Channel Control Bits to the Output Streams (Non-32 Mb/s Mode) MT90869 Channel No 3-2 3 etc etc etc etc etc etc etc etc etc etc Ch 254 Ch 127 254 Ch 127 255 Ch 127 255 Ch 127 255 Ch 127 33 Zarlink Semiconductor Inc. Data Sheet 2 4 Mb Frame Boundary etc etc etc etc ...
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... Note 3-1 to 3-4: See Section 4.2.1 for examples of Channel Control Bit for streams of different data-rates. MT90869 Channel No 255 Ch 127 255 Ch 127 255 Ch 127 255 Ch 127 255 Ch 127 etc etc etc etc 34 Zarlink Semiconductor Inc. Data Sheet 2 4 Mb Frame Boundary etc etc ...
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... Backplane Connection Memory Bit Definition for setting the Backplane Output Enable Bit (BE). MT90869 Channel 255 bits 7 Chan 0 Chan 0 Chan 127 Chan 127 Bit 5 Bit 4 Bit 3 Chan 0 Bit 6 Chan 63 Bit 1 One C16o period 35 Zarlink Semiconductor Inc. Data Sheet Chan 127 Chan 127 Chan 0 Bit 2 Bit 1 Bit 0 Bit 7 Chan 0 Chan 63 Bit 0 Bit 7 Chan 0 ...
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... Table 4 - BCSTo Allocation of Channel Control Bits to the Output Streams (32 Mb/s Mode) MT90869 Allocated Stream No. BCSTo1 BCSTo2 BCSTo3 3-2 3-2 3 Zarlink Semiconductor Inc. Data Sheet 2 Channel No. 32 Mb/s Ch 511 Ch 511 Ch 511 Ch 511 ...
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... Table 4 - BCSTo Allocation of Channel Control Bits to the Output Streams (32 Mb/s Mode) MT90869 Channel No. BCSTo2 BCSTo3 32 Mb etc etc etc etc etc etc etc etc Ch 508 508 509 509 509 509 510 510 510 510 511 511 37 Zarlink Semiconductor Inc. Data Sheet 2 Frame Boundary ...
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... Note 2: The Channel Numbers presented relate to the specific stream operating at a data-rate of 32.768Mb/s. Note 3-1 to 3-4: See Section 4.2.2 for examples of Channel Control Bits. MT90869 Channel No. BCSTo2 BCSTo3 32 Mb 511 511 etc etc etc 38 Zarlink Semiconductor Inc. Data Sheet 2 Frame Boundary ...
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... Channel 1 Channel 510 bits 7-0 bits 7-0 Channel 1 Channel 510 bits 7-0 bits 7-0 39 Zarlink Semiconductor Inc. Data Sheet Channel 511 bits 7-0 Channel 511 bits 7-0 Channel 511 bits 7-0 Channel 511 bits 7-0 One C16o cycle ...
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... Figure 16 - Constant Switch Delay: Examples of different stream rates and routing MT90869 Frames N+1 and N+2 Frame N 254 255 254 255 127 CH CH 127 CH CH 127 127 511 254 255 0 40 Zarlink Semiconductor Inc. Data Sheet Frame N 254 255 254 255 127 127 127 127 ...
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... Zarlink Semiconductor Inc. Data Sheet [7:0] [7:0] [7:0] [7:0] [8:0] ...
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... DTA handshake when accessed but any data read from the bus will be invalid. There must be a minimum between CPU accesses, to allow the MT90869 device to recognize the accesses as separate (i.e., a minimum must separate the de-assertion of DTA (to high) and the assertion of CS and/ initiate the next access). MT90869 Zarlink Semiconductor Inc. Data Sheet ...
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... The stream, channel number and the number of consecutive channels following the start channel are similarly allocated for the receiver and detection of the PRBS. Examples of a channel sequence are presented in Figure 17. MT90869 43 Zarlink Semiconductor Inc. Data Sheet ...
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... Note: Length = Start Chan. + No. of Consecutive channels Once Started BER transmission continues until stopped by the BER control register:- FP stream Figure 17 - Examples of BER transmission channels MT90869 ...... ..... ..... ..... 254 3 ..... ..... 1 2 ...... ..... 254 ...... ..... ..... ..... 254 Channels containing data (traffic) 44 Zarlink Semiconductor Inc. Data Sheet 255 255 0 2 255 ...
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... Test Data Register to operate while the instruction is current, and to define the serial Test Data Register path to shift data between TDi and TDo during data register scanning. MT90869 45 Zarlink Semiconductor Inc. Data Sheet -core when not ...
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... Manufacturer ID, Bits <11:1>:0001 0100 101 Header, Bit <0> (LSB):1 11.3 Boundary Scan Description Language (BSDL) File A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the IEEE 1149.1 test interface. 12.0 Memory Address Mappings Address Bit ...
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... When HIGH, the channel is in Message Mode Local Output Enable Bit When LOW the channel may be high impedance, either at the device output, or set by an external buffer dependent upon the LORS pin. When HIGH the channel is active. MT90869 Description Description Description 47 Zarlink Semiconductor Inc. Data Sheet . ...
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... Bit BSRC selects the switch configuration for Local-to-Backplane or Backplane-to-Backplane. When the per- channel Message Mode is selected (BMM = HIGH), the lower byte of the BCM word (BCAB7-0) will be transmitted as data on the output stream (BSTo0-31) in place of data defined by the Source Control, Stream Address and Channel Address bits. MT90869 Description Description 48 Zarlink Semiconductor Inc. Data Sheet ...
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... Source Channel Address Bits. The binary value of these 9 bits represents the input channel number when BMM is LOW. BCAB7-0 are transmitted as data when BMM is set HIGH in Message Mode. Table 14 - BCM Bits for Backplane-to-Backplane Switching (32Mb/s mode) MT90869 Description Mode) Description 49 Zarlink Semiconductor Inc. Data Sheet ...
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... Backplane Input Bit rate Register 0, BIBRR0 - Register 31, BIBRR31 012D 014C Backplane Output Bit rate Register 0, BOBRR0 - Register 31, BOBRR31 014D Memory BIST Register, MBISTR H 3FFF Revision control register, RCR H Table 15 - Address Map for Register (A14 = 0) MT90869 Register 50 Zarlink Semiconductor Inc. Data Sheet ...
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... LCSTo0-3 are driven low. When HIGH, the BSTo0-31, LSTo0-31, BCSTo0-3 and LCSTo0-3 are enabled. MT90869 Description ODE Pin OSB bit BSTo0 - 31, LSTo0 - Output Control with ODE pin and OSB bit Table 16 - Control Register Bits 51 Zarlink Semiconductor Inc. Data Sheet Disable Disable Enable ...
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... Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (b) Frame Pulse Width = 244 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i Figure 18 - Frame Boundary Conditions, ST- BUS Operation MT90869 Description Table 16 - Control Register Bits Frame Boundary 52 Zarlink Semiconductor Inc. Data Sheet ...
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... MBP bit in the Control Register (CR) is set HIGH and the BPE is set HIGH, the contents of Bits BBPD2-0 are loaded into Bits 15-13, respectively, of the BCM. Bits 12-0 of the BCM are set LOW. MT90869 Frame Boundary Description 53 Zarlink Semiconductor Inc. Data Sheet . ...
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... BER Mode Select for Backplane. When set HIGH, a PRBS sequence of length 2 Backplane port. When set LOW, a PRBS sequence of length 2 for the Backplane port. Table 18 - Bit Error Rate Test Control Register (BERCR) Bits MT90869 Description Description 54 Zarlink Semiconductor Inc. Data Sheet selected for the selected ...
Page 55
... Table 19 - Local Channel Delay Register (LCDRn) Bits MT90869 Description Reset 0 Reserved 0 Local Channel Delay Register The binary value of these bits refers to the channel delay value for the local input stream. 55 Zarlink Semiconductor Inc. Data Sheet selected for the Local selected for the Description : ...
Page 56
... Channels 1111 1101 254 Channels 1111 1110 255 Channels 1111 1111 Reset 0 Reserved 0 Local Input Bit Delay Register The binary value of these bits refers to the input bit delay value for the local input stream 56 Zarlink Semiconductor Inc. Data Sheet ... ... Description ...
Page 57
... Table 22, “Local Input Bit Delay Programming Table,” on page 57, illustrates the bit delay selection. Data Rate LID4 0 (Default) 0 1/4 0 1 3/4 1 Table 22 - Local Input Bit Delay Programming Table MT90869 1 / bit period Corresponding Delay Bits LID3 LID2 Zarlink Semiconductor Inc. Data Sheet LID1 LID0 ...
Page 58
... Reset 0 Reserved 0 Backplane Channel Delay Register The binary value of these bits refers to the channel delay value for the backplane input stream Corresponding Delay Bits 58 Zarlink Semiconductor Inc. Data Sheet Description BCD8-BCD0 0 0000 0000 0 0000 0001 0 0000 0010 0 0000 0011 0 0000 0100 0 0000 0101 ...
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... Reset Reserved 0 Reserved BID(4:0) 0 Backplane Input Bit Delay Register The binary value of these bits refers to the input bit delay value for the backplane input stream Corresponding Delay Bits BID4 BID3 BID2 Zarlink Semiconductor Inc. Data Sheet Description 3 / bit periods BID1 BID0 ...
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... The LOAR0 to LOAR31 registers are configured as follows: LOARn Bit Name (where 31) 15-2 Reserved 1-0 LOA(1:0) Table 27 - Local Output Advancement Register (LOARn) Bits MT90869 Corresponding Delay Bits BID4 BID3 BID2 Reset 0 Reserved 0 Local Output Advancement Register 60 Zarlink Semiconductor Inc. Data Sheet BID1 BID0 Description ...
Page 61
... Table 30 - Backplane Output Advancement (BOAR) Programming Table MT90869 Corresponding Advancement Bits LOA1 Name Reset Reserved 0 Reserved BOA(1:0) 0 Backplane Output Advancement Register Backplane Output Advancement For 32 Mb/s clock Rate 131.072 MHz 0 (Default) -1 cycle -2 cycle -3 cycle 61 Zarlink Semiconductor Inc. Data Sheet LOA0 Description Corresponding Advancement Bits BOA1 BOA0 ...
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... The binary value of these bits refers to the local output stream which carries the BER data. 0 Local BER Send Channel Address Bits. The binary value of these bits refers to the local output channel in which the BER data starts to be sent. Description 62 Zarlink Semiconductor Inc. Data Sheet ...
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... Local BER Receive Channel Address Bits The binary value of these bits refers to the local input channel in which the BER data starts to be compared. Description Local Bit Error Rate Count The binary value of the bits define the Local Bit Error count. 63 Zarlink Semiconductor Inc. Data Sheet ...
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... The binary value of these bits define the backplane output stream to transmit the BER data. Backplane BER Send Channel Address Bits The binary value of these bits define the backplane output Start Channel in which the BER data is transmitted. Description Description 64 Zarlink Semiconductor Inc. Data Sheet ...
Page 65
... Reserved 1-0 LIBR(1:0) Table 41 - Local Input Bit Rate Register (LIBRRn) Bits MT90869 Description Description Backplane Bit Error Rate Count The binary value of these bits define the Backplane Bit Error count. 0 Reserved 0 Local Input Bit Rate 65 Zarlink Semiconductor Inc. Data Sheet Description ...
Page 66
... Table 45 - Backplane Input Bit Rate Register (BIBRRn) Bits MT90869 LIBR0 Bit rate for stream Mb/s Reset 0 Reserved 0 Local Output Bit Rate LOBR0 Bit rate for stream Mb/s Reset 0 Reserved 0 Backplane Input Bit Rate 66 Zarlink Semiconductor Inc. Data Sheet Description Description ...
Page 67
... MBIST. The first with only Bit 12 (LV_TM) set High (i.e., 1000h), the second with Bit 12 maintained High but with the required start bit(s) set High. MT90869 BIBR0 Bit rate for stream Mb/s Reset 0 Reserved 0 Backplane Output Bit Rate BOBR0 Bit rate for stream Mb/s 67 Zarlink Semiconductor Inc. Data Sheet Description ...
Page 68
... High indicates completion of Memory BIST sequence. 0 BISTPCL 0 Local Connection Memory Pass/Fail Bit (Read only). This bit indicates the Pass/Fail status following completion of the Memory BIST sequence. A HIGH indicates Pass, a LOW indicates Fail. Table 49 - Memory BIST Register (MBISTR) Bits MT90869 Description 68 Zarlink Semiconductor Inc. Data Sheet ...
Page 69
... The revision control register stores the binary value of the silicon revision number. This register is read only. The RCR register is configured as follows: Bit Name Reset Value 15-4 Reserved 3-0 RC(3:0) defined by silicon Table 50 - Revision Control Register (RCR) Bits MT90869 0 Reserved. Revision Control Bits 69 Zarlink Semiconductor Inc. Data Sheet Description ...
Page 70
... DD_PLL V -0 -0.5 I_5V Sym. Min. Typ 3.0 3.3 DD_IO V 1.62 1.8 DD_CORE V 1.62 1.8 DD_PLL I_5V 70 Zarlink Semiconductor Inc. Data Sheet Max. Units 2.5 V 5 +0.5 V DD_IO 7 C +125 Max. Units C +85 3.6 V 1. DD_IO 5.5 V ...
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... Sym. Level Units V 0.5V V 3.0V < DD_IO V 0.7V V 3.0V < DD_IO V 0.3V V 3.0V < DD_IO 71 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions mA Static I and DD _Core PLL current mA Applied clock C8i = 8.192 MHz A Static I DD _IO mA I with all output AV streams at max. data-rate ...
Page 72
... LCH8 t 59 LCL8 rLC8o fLC8o t 62 FPW16 t -29 FODF16 t 30 FODR16 t 62 LCP16 t 29 LCH16 t 30 LCL16 rLC16o fLC16o 72 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes 350 ns 220 220 110 ns 110 110 110 ns 110 110 124 7.5 ns 127 ns 127 C =60pF ...
Page 73
... CK_int is the internal clock signal of 131.072MHz Figure 20 - Backplane and Local Clock Timing Diagram for ST-BUS MT90869 t BFPW244 t BFPH244 t BFPW122 t BFPH122 t BCP8 t fBC8i t LFBOS t LFPW8_244 t FODR8_244 t LFPW8 t t LFODF8 LFODR8 t t LCL8 LCP8 t fLC8o t FPW16 t FODR16 t LCP16 t fLC16o 73 Zarlink Semiconductor Inc. Data Sheet t rBC8i t rLC8o t rLC16o ...
Page 74
... Figure 21 - Backplane and Local Clock Timing for GCI-BUS MT90869 t BGFPW t t BGFPS BGFPH t BCP8 t t BCL8 BCH8 t t fBC8i rBC8i t LFBOS t GFPW8 t t GFPS8o GFPH8o t t LCH8 LCP8 t FPW16 t FRH16o t LCP16 t rLC16o 74 Zarlink Semiconductor Inc. Data Sheet t t rLC8o fLC8o t fLC16o ...
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... BIDS4 t BSIS4 t BSIH4 Bit7 Bit6 Ch0 Ch0 t BSOD4 Bit7 Bit6 Ch0 Ch0 t BIDS2 t BSIS2 t BSIH2 Bit7 Ch0 t BSOD2 Bit7 Ch0 75 Zarlink Semiconductor Inc. Data Sheet Typ. Max. Units Notes With zero offset 183 188 366 371 =50pF L 10.5 10.5 10.5 10 ...
Page 76
... MT90869 t BIDS32 t BSIS32 t BSIH32 BSOD32 Bit7 Bit6 Bit5 Bit0 Ch0 Ch0 Ch0 Ch511 t BIDS16 t BSIS16 t BSIH16 Bit7 Bit0 Ch0 t BSOD16 Bit7 Ch0 76 Zarlink Semiconductor Inc. Data Sheet Bit4 Bit2 Bit3 Ch0 Ch0 Ch0 Bit6 Bit5 Ch0 Ch0 Bit5 Bit6 Ch0 Ch0 ...
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... BSIH4 Bit0 Bit1 Ch0 Ch0 t BSOD4 Bit0 Bit1 Ch0 Ch0 t BIDS2 t BSIS2 t BSIH2 Bit0 Ch0 t BSOD2 Bit0 Ch0 77 Zarlink Semiconductor Inc. Data Sheet Bit5 Bit6 Bit4 Ch0 Ch0 Ch0 Bit2 Bit3 Ch0 Ch0 Bit2 Bit3 Ch0 Ch0 Bit1 Ch0 Bit1 Ch0 ...
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... LSIS2 t 3 LSIH16 t 3 LSIH8 t 3 LSIH4 t 3 LSIH2 t 0 LSOD16 t 0 LSOD8 t 0 LSOD4 t 0 LSOD2 78 Zarlink Semiconductor Inc. Data Sheet Bit3 Bit5 Bit4 Ch0 Ch0 Ch0 Bit1 Bit2 Ch0 Ch0 Bit2 Bit1 Ch0 Ch0 Max. Units Notes 7 With zero 97 offset ...
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... LSTo0 - 31 Bit0 Ch255 16.384 Mb/s * CK_int is the internal clock signal of 131.072 MHz Figure 26 - ST-BUS Local Timing Diagram (16 Mb/s) MT90869 t LFBOS t LIDS16 t LSIS16 t LSIH16 Bit7 Bit6 Ch0 Ch0 t LSOD16 Bit6 Bit7 Ch0 Ch0 79 Zarlink Semiconductor Inc. Data Sheet Bit5 Ch0 Bit5 Ch0 ...
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... LSOD2 Bit7 Ch0 Sym. Min. Typ. Max ODE t 14 ODZ = 1k//1k potential divider, with timing corrected for Zarlink Semiconductor Inc. Data Sheet Bit2 Bit3 Bit1 Ch0 Ch0 Ch0 Bit5 Bit4 Ch0 Ch0 Bit5 Bit4 Ch0 Ch0 Bit6 Ch0 Bit6 Ch0 Unit ...
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... RWS t 8 ADS t 0 CSH t 8 RWH t 8 ADH t 14 DDR t DHR t 8 WDS t 8 DHW t AKD t AKH = 1k//1k potential divider, with timing corrected to cancel L 81 Zarlink Semiconductor Inc. Data Sheet VTT VTT Unit Max. Test Conditions =60pF =60pF Note =60pF ...
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... DTA (to high) and the assertion of CS and/or DS (to initiate the next access). MT90869 t CSS t RWS t ADS VALID ADDRESS VALID READ DATA t WDS VALID WRITE DATA t DDR t AKD 82 Zarlink Semiconductor Inc. Data Sheet CSH RWH ADH DHR V ...
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