XC2S600E-6FG676C Xilinx Inc, XC2S600E-6FG676C Datasheet

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R DS077 June 18, 2008 This document includes all four modules of the Spartan Module 1: Introduction and Ordering Information DS077-1 (v2.3) June 18, 2008 • Introduction • Features • General Overview • Product Availability • User I/O Chart • ...

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R DS077 June 18, 2008 Product Specification ...

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... XC2S300E 6,912 93,000 - 300,000 XC2S400E 10,800 145,000 - 400,000 XC2S600E 15,552 210,000 - 600,000 Notes: 1. User I/O counts include the four global clock/user input pins. See details in © 2003-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners ...

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... Loops (DLLs), one at each corner of the die. Two columns of block RAM lie on opposite sides of the die, between the CLBs and the IOB columns. The XC2S400E has four col- umns and the XC2S600E has six columns of block RAM. These functional elements are interconnected by a powerful hierarchy of versatile routing channels (see Spartan-IIE FPGAs are customized by loading configura- tion data into internal static memory cells ...

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... XC2S150E 265 XC2S200E 289 XC2S300E 329 XC2S400E 410 XC2S600E 514 Notes: 1. User I/O counts include the four global clock/user input pins. DS077-1 (v2.3) June 18, 2008 Product Specification Spartan-IIE FPGA Family: Introduction and Ordering Information Available User I/O According to Package Type ...

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... Device Speed Grade XC2S50E -6 Standard Performance XC2S100E -7 Higher Performance XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E Notes: 1. The -7 speed grade is exclusively available in the Commercial temperature range. 2. See www.xilinx.com for information on automotive temperature range devices. Device Part Marking Figure top marking example for Spartan-IIE FPGAs in the quad-flat packages ...

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... Updated -7 availability. 11/18/02 2.0 Added XC2S400E and XC2S600E. Corrected XC2S150E max I/O count and XC2S50E differential I/O count and updated availability. 07/09/03 2.1 Noted hot-swap capability. Updated Table 2 to show that all products are available. Clarified device part marking. ...

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Spartan-IIE FPGA Family: Introduction and Ordering Information 8 www.xilinx.com R DS077-1 (v2.3) June 18, 2008 Product Specification ...

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R DS077-2 (v2.3) June 18, 2008 Architectural Description Spartan-IIE FPGA Array ® The Spartan -IIE user-programmable gate array, shown in Figure 3, is composed of five major configurable elements: • IOBs provide the interface between the package pins and the ...

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Spartan-IIE FPGA Family: Functional Description TFF OFF IFF Table 3: Standards Supported by I/O (Typical Values) Input Reference Input Voltage Voltage I/O Standard ( REF CCO LVTTL (2-24 mA) N/A 3.3 LVCMOS2 N/A 2.5 LVCMOS18 N/A 1.8 PCI ...

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R Optional pull-up and pull-down resistors and an optional weak-keeper circuit are attached to each user I/O pad. Prior to configuration all outputs not involved in configuration are forced into their high-impedance state. The pull-down resis- tors and the weak-keeper ...

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... FPGA. The hot swap functionality XC2S400E, and XC2S600E device. All other Spartan-IIE devices built after Product Change Notice include hot swap functionality. To support hot swap, Spartan-IIE devices include the follow- ing I/O features. • ...

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R Configurable Logic Block The basic building block of the Spartan-IIE FPGA CLB is the logic cell (LC includes a 4-input function generator, carry logic, and storage element. The output from the func- tion generator in each LC ...

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Spartan-IIE FPGA Family: Functional Description Figure 6: Spartan-IIE CLB Slice (two identical slices in each CLB) Additional Logic The F5 multiplexer in each slice combines the function gen- erator outputs (Figure 7). This combination provides either a function generator that ...

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... Spartan-IIE devices contain two such columns, one along each vertical edge. The XC2S400E has four block RAM col- umns and the XC2S600E has six block RAM columns. These columns extend the full height of the chip. Each memory block is four CLBs high, and consequently, a Spartan-IIE device 16 CLBs high will contain four memory blocks per column, and a total of eight blocks ...

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Spartan-IIE FPGA Family: Functional Description Table 7 shows the depth and width aspect ratios for the block RAM. Table 7: Block RAM Port Aspect Ratios Width Depth ADDR Bus 1 4096 ADDR<11:0> 2 2048 ADDR<10:0> 4 1024 ADDR<9:0> 8 512 ...

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R Dedicated Routing Some classes of signal require dedicated routing resources to maximize performance. In the Spartan-IIE FPGA archi- tecture, dedicated routing resources are provided for two classes of signal. CLB Figure 10: BUFT Connections to Dedicated Horizontal Bus Lines ...

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Spartan-IIE FPGA Family: Functional Description edges arrive at internal flip-flops in synchronism with clock edges arriving at the input. CLKOUT Variable CLKIN Delay Line Control CLKFB Figure 12: Delay-Locked Loop Block Diagram In addition to eliminating clock-distribution delay, the DLL ...

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R Table 8: Boundary-Scan Instructions (Continued) Boundary-Scan Binary Command Code[4:0] INTEST 00111 Enables boundary-scan USERCODE 01000 IDCODE 01001 Enables shifting out of HIGHZ 01010 JSTART 01100 BYPASS 11111 RESERVED All other codes IOB IOB IOB IOB IOB IOB IOB IOB ...

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... XXXX XC2S200E XXXX XC2S300E XXXX XC2S400E XXXX XC2S600E XXXX Development System Spartan-IIE FPGAs are supported by the Xilinx ISE tools. The basic methodology for Spartan-IIE FPGA design consists of three interrelated steps: design entry, imple- mentation, and verification. Industry-standard tools are used for design entry and simulation, while Xilinx provides proprietary architecture-specific tools for implementation ...

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... FLASH cards, and so on) can be used. Table 10: Spartan-IIE Configuration File Size Device Configuration File Size (Bits) XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E Modes Spartan-IIE devices support the following four configuration modes: • Slave Serial mode • Master Serial mode • Slave Parallel mode • ...

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Spartan-IIE FPGA Family: Functional Description Table 11: Configuration Modes Preconfiguration Configuration Mode Pull-ups Master Serial mode Slave Parallel mode (SelectMAP) Boundary-Scan mode Slave Serial mode Notes: 1. During power-on and throughout configuration, the I/O drivers will high-impedance ...

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R Configuration Configuration During at Power-up User Operation V CCO No AND V CCINT High? Yes FPGA Drives INIT and DONE Low Clear Configuration Memory Yes User Holding PROGRAM Low? No Yes User Holding INIT Low? No FPGA Samples Mode ...

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Spartan-IIE FPGA Family: Functional Description During start-up, the device performs four operations: 1. The assertion of DONE. The failure of DONE to go High may indicate the unsuccessful loading of configuration data. 2. The release of the Global Three State ...

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... FPGAs are High. For more information, see Start-up, page The maximum amount of data that can be sent to the DOUT pin for a serial daisy chain 33,554,400 bits, which is approximately 8 XC2S600E bit- streams. The configuration bitstream of downstream shows connections for devices is limited to this size. ...

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Spartan-IIE FPGA Family: Functional Description Master Serial Mode In Master Serial mode, the CCLK output of the FPGA drives a Xilinx PROM, which feeds a serial stream of configuration data to the FPGA’s DIN input. Figure 19 Serial FPGA configuring ...

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R DATA[7:0] CCLK WRITE BUSY CS(0) DONE INIT PROGRAM Figure 20: Slave Parallel Configuration Circuit Diagram Multiple Spartan-IIE FPGAs can be configured using the Slave Parallel mode, and be made to start-up simulta- neously. To configure multiple devices in this ...

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Spartan-IIE FPGA Family: Functional Description If CCLK is slower than F , the FPGA will never assert CCNH BUSY. In this case, the above handshake is unnecessary, and data can simply be entered into the FPGA every CCLK cycle. After ...

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... Revision History Version No. Date 1.0 11/15/01 Initial Xilinx release. 2.0 11/18/02 Added XC2S400E and XC2S600E. Removed Preliminary designation. Clarified details of I/O standards, boundary scan, and configuration. 2.1 07/09/03 Added hot swap description (see Table 9 2.3 06/18/08 Added note that TDI, TMS, and TCK have a default pull-up resistor. Add note on maximum daisy-chain limit ...

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Spartan-IIE FPGA Family: Functional Description 30 www.xilinx.com R DS077-2 (v2.3) June 18, 2008 Product Specification ...

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R DS077-3 (v2.3) June 18, 2008 Definition of Terms In this document, some specifications may be designated as Advance or Preliminary. These designations are based on the more detailed timing information used by the development system and reported in the ...

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... XC2S50E Commercial Industrial XC2S100E Commercial Industrial XC2S150E Commercial Industrial XC2S200E Commercial Industrial XC2S300E Commercial Industrial XC2S400E Commercial Industrial XC2S600E Commercial Industrial (1) pin TQ, PQ, FG, FT packages = 0V 3.3V IN CCO = 3.6V (sample tested) IN www.xilinx.com Min Max 0 85 –40 100 1.8 – 1.8 – ...

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... Devices after the PCN have a ‘T’ preceding the date code as referenced in the PCN. Note that the XC2S150E, XC2S400E, and XC2S600E always have this mark. Devices before the PCN have an ‘S’ preceding the date code. Note that devices before the PCN are ...

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Spartan-IIE FPGA Family: DC and Switching Characteristics V Input/Output IL Standard V, Min V, Max HSTL I –0.5 V REF HSTL III –0.5 V REF HSTL IV –0.5 V REF SSTL3 I –0.5 V REF SSTL3 II –0.5 V REF ...

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... Values apply to all Spartan-IIE devices unless otherwise noted. Description Constants for Calculating TIOOP 42. Device XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E Constants for Calculating TIOOP 42. www.xilinx.com (1) Speed Grade All -7 -6 Min Max Max 1.0 3 ...

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... For a global clock input with standards other than LVTTL, adjust delays with values from the Global Clock Input Adjustments, page 36 Description (1) with DLL 42. Device XC2S50E XC2S100E (1) XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E 42. www.xilinx.com Speed Grade -7 -6 Min Min Units 1 1 IOB Input Delay Adjustments for Different I/O Standard Speed Grade ...

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... Description Device All All All XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E All All XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E All All All All www.xilinx.com Speed Grade -7 -6 Min Max Min Max 0.4 0.8 0.4 0.8 0.5 1.0 0.5 1.0 ...

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Spartan-IIE FPGA Family: DC and Switching Characteristics IOB Input Delay Adjustments for Different Standards Input delays associated with the pad are specified for LVTTL. For other standards, adjust the delays by the values shown. A delay adjusted in this way ...

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R IOB Output Switching Characteristics Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in Symbol Propagation Delays T O input ...

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Spartan-IIE FPGA Family: DC and Switching Characteristics IOB Output Delay Adjustments for Different Standards(1) Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by the ...

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R Calculation Function of IOOP Capacitance T is the propagation delay from the O Input of the IOB IOOP to the pad. The values for T are based on the standard IOOP capacitive load (C ) ...

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Spartan-IIE FPGA Family: DC and Switching Characteristics Clock Distribution Switching Characteristics T is specified for LVTTL levels. For other standards, adjust T GPIO Input Adjustments. Symbol GCLK IOB and Buffer T Global clock pad to output GPIO T Global clock ...

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R DLL Timing Parameters Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect Symbol Description F Input clock frequency (CLKDLLHF) CLKINHF F Input clock frequency (CLKDLL) ...

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Spartan-IIE FPGA Family: DC and Switching Characteristics Period Tolerance: the allowed input clock period change in nanoseconds CLKIN F CLKIN Output Jitter: the difference between an ideal reference clock edge and the actual design. Ideal Period Actual Period ...

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R CLB Switching Characteristics Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise values are provided by the timing analyzer. Symbol Combinatorial Delays T 4-input function: F/G inputs to X/Y ...

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Spartan-IIE FPGA Family: DC and Switching Characteristics CLB Arithmetic Switching Characteristics Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. Precise values are provided by the timing analyzer. Symbol Combinatorial ...

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R CLB Distributed RAM Switching Characteristics Symbol Sequential Delays T Clock CLK to X/Y outputs (WE active mode) SHCKO16 T Clock CLK to X/Y outputs (WE active mode) SHCKO32 Setup/Hold Times with Respect to ...

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Spartan-IIE FPGA Family: DC and Switching Characteristics TBUF Switching Characteristics Symbol T IN input to OUT output IO T TRI input to OUT output high impedance OFF T TRI input to valid data on OUT output ON JTAG Test Access ...

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R DIN CCLK DOUT (Output) . Symbol T / DCC T CCD T CCO T CCH T CCL F CC CCLK (Output) Serial Data In Serial DOUT (Output) . Symbol T / DSCK T CKDS T CCLK CCO F CC ...

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Spartan-IIE FPGA Family: DC and Switching Characteristics CCLK CS WRITE T SMCCW T SMDCC DATA[7:0] T SMCKBY BUSY No Write Symbol T / SMDCC T SMCCD T / SMCSCC T SMCCCS T / CCLK SMCCW T SMWCC T SMCKBY F ...

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... Initial Xilinx release. 1.1 06/28/02 Added -7 speed grade and extended DLL specs to Industrial. 2.0 11/18/02 Added XC2S400E and XC2S600E. Added minimum specifications. Added reference to XAPP450 for Power-On Requirements. Removed Preliminary designation. 2.1 07/09/03 Added TCCPO applications. Updated 2.3 06/18/08 Updated I/O measurement thresholds ...

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Spartan-IIE FPGA Family: DC and Switching Characteristics 52 www.xilinx.com R DS077-3 (v2.3) June 18, 2008 Product Specification ...

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R DS077-4 (2.3) June 18, 2008 Introduction This section describes how the various pins on a ® Spartan -IIE FPGA connect within the supported component packages, and provides device-specific thermal characteristics. Spartan-IIE FPGAs are available in both standard and Pb-free, ...

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Spartan-IIE FPGA Family: Pinout Tables Pin Definitions (Continued) Dedicated Pad Name Pin D0/DIN, D1, D2, D3, No D4, D5, D6, D7 WRITE TDI, TDO, TMS, TCK Yes V Yes CCINT V Yes CCO V No REF GND ...

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R Spartan-IIE Package Pinouts ® The Spartan -IIE family of FPGAs is available in five popu- lar, low-cost packages, including plastic quad flat packs and fine-pitch ball grid arrays. Family members have footprint compatibility across devices provided in the same ...

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... XC2S300E XC2S400E XC2S600E XC2S400E FG676 FGG676 XC2S600E 56 value similarly reports the difference between the board and junction temperature. The junction-to-ambient (θ reports the temperature difference between the ambient environment and the junction temperature. The θ reported at different air velocities, measured in linear feet per minute (LFM). The “ ...

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... XC2S300E - 50 XC2S400E - - XC2S600E - - Synchronous or Asynchronous I/O pins for differential signals can either be synchronous or asynchronous, input or output. Differential signaling requires the pins of each pair to switch simultaneously. If the output signals driving the pins are from IOB flip-flops, they are synchronous. If the signals driving the pins are from internal logic, they are asynchronous, and therefore more care must be taken that they are simultaneous ...

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Spartan-IIE FPGA Family: Pinout Tables Pinout Tables The following device-specific pinout tables include all pack- ages available for each Spartan-IIE device. They follow the pad locations around the die. In the TQ144 package, all VCCO pins must be connected to ...

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R TQ144 Pinouts (XC2S50E and XC2S100E) (Continued) Pad Name Function Bank Pin I/O (DLL), L17P 4 P56 I/O 4 P57 I/O, VREF 4 P58 Bank 4 I/O, L16N_YY 4 P59 I/O, L16P_YY 4 P60 VCCINT - P61 GND - P62 ...

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Spartan-IIE FPGA Family: Pinout Tables TQ144 Pinouts (XC2S50E and XC2S100E) (Continued) Pad Name Function Bank Pin I/O (CS), 1 P112 L5P_YY I/O (WRITE), 1 P113 L5N_YY I/O 1 P114 I/O, VREF 1 P115 Bank 1 I/O 1 P116 I/O, L4P_YY ...

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R In the PQ208 package, all VCCO pins must be connected to the same voltage. PQ208 Pinouts (XC2S50E, XC2S100E, XC2S150E, XC2S200E, XC2S300E) Pad Name LVDS Async. Output Function Bank Pin Option GND - P1 TMS - P2 I ...

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Spartan-IIE FPGA Family: Pinout Tables PQ208 Pinouts (XC2S50E, XC2S100E, XC2S150E, XC2S200E, XC2S300E) Pad Name LVDS Async. Output Function Bank Pin Option I/O, VREF 6 P45 XC2S100E, Bank 6, 150E L39P I/O, L39N 6 P46 XC2S100E, 150E I/O 6 P47 I/O, ...

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R PQ208 Pinouts (XC2S50E, XC2S100E, XC2S150E, XC2S200E, XC2S300E) Pad Name LVDS Async. Output Function Bank Pin Option I/O, L28P 4 P89 XC2S50E, 100E, 200E, 300E VCCINT - P90 VCCO - P91 GND - P92 I/O, L27N 4 P93 XC2S50E, 100E, ...

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Spartan-IIE FPGA Family: Pinout Tables PQ208 Pinouts (XC2S50E, XC2S100E, XC2S150E, XC2S200E, XC2S300E) Pad Name LVDS Async. Output Function Bank Pin Option I/O 2 P134 I/O (D3), 2 P135 XC2S50E, L17N 300E I/O, VREF 2 P136 XC2S50E, Bank 2, 300E L17P ...

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R PQ208 Pinouts (XC2S50E, XC2S100E, XC2S150E, XC2S200E, XC2S300E) Pad Name LVDS Async. Output Function Bank Pin Option I/O, VREF 1 P178 XC2S50E, Bank 1, L6P 200E, 300E I/O, L6N 1 P179 XC2S50E, 200E, 300E I/O 1 P180 I/O (DLL), 1 ...

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Spartan-IIE FPGA Family: Pinout Tables FT256 Pinouts (XC2S50E, XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E) Pad Name Function Bank Pin TMS - B1 I I/O, L83P 7 C2 XC2S100E, I/O, L83N 7 C1 XC2S100E, I/O, L82P_YY 7 D2 I/O, L82N_YY ...

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R FT256 Pinouts (XC2S50E, XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E) (Continued) Pad Name Function Bank Pin I/O, L65P 6 L4 XC2S50E, 150E, 200E, 300E, 400E I/O, VREF 6 L5 XC2S50E, Bank 6, L65N 150E, 200E, 300E, 400E I/O, L64P_YY 6 M3 ...

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Spartan-IIE FPGA Family: Pinout Tables FT256 Pinouts (XC2S50E, XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E) (Continued) Pad Name Function Bank Pin I/O, L51P 4 N9 XC2S50E, 150E, 200E, I/O, L50N 4 T10 XC2S50E, 200E, 300E, XC2S50E, I/O, VREF 4 R10 200E, 300E, ...

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R FT256 Pinouts (XC2S50E, XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E) (Continued) Pad Name Function Bank Pin I/O (D5), 3 L13 L35N_YY I/O, L35P_YY 3 K14 I/O, L34N 3 K15 XC2S100E, 150E, 400E I/O, L34P 3 K16 XC2S100E, 150E, 400E I/O, L33N ...

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Spartan-IIE FPGA Family: Pinout Tables FT256 Pinouts (XC2S50E, XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E) (Continued) Pad Name Function Bank Pin I/O, L20P 2 D14 XC2S100E, 200E, 300E I/O (DIN, D0), 2 B16 L19N_YY I/O (DOUT, 2 C15 BUSY), L19P_YY CCLK 2 ...

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R FT256 Pinouts (XC2S50E, XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E) (Continued) Pad Name Function Bank Pin I/O, L6P 0 C7 XC2S50E, 200E, 300E, I/O, L6N 0 B7 XC2S50E, 200E, 300E, I I/O, L5P 0 B6 XC2S50E, 100E, 200E, 300E, ...

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Spartan-IIE FPGA Family: Pinout Tables Additional FT256 Package Pins (Continued) VCCO Bank 5 Pins VCCO Bank 6 Pins VCCO Bank 7 Pins GND Pins A1 A16 B2 F11 ...

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... R FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E) Pad Name LVDS Async. Output Function Bank Pin Option TMS - XC2S150E I I XC2S150E I/O, L#P_Y 7 D2 XC2S150E, 200E, 300E, 400E I/O, L#N_Y 7 D1 XC2S150E, 200E, 300E, 400E I/O, L#P_Y 7 E2 XC2S100E, 200E, 300E, ...

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... Spartan-IIE FPGA Family: Pinout Tables FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E) Pad Name LVDS Async. Output Function Bank Pin Option I I/O, VREF 7 H3 XC2S300E, Bank 7, 400E, 600E L#P_Y I/O, L#N_Y 7 H4 XC2S300E, 400E, 600E I/ All L#P_YY I/ All L#N_YY I/O ...

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... R FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E) Pad Name LVDS Async. Output Function Bank Pin Option I/ All L#P_YY I/O (IRDY All L#N_YY I/O (TRDY I I/O, L#P_Y 6 M3 XC2S200E, 300E, 600E I/O, L#N_Y 6 M4 XC2S100E, 150E, 200E, 300E, 600E I/O, L#P_Y ...

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... Spartan-IIE FPGA Family: Pinout Tables FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E) Pad Name LVDS Async. Output Function Bank Pin Option I/O, L#P_Y 6 R2 XC2S300E, 400E, 600E I/O, VREF 6 R3 XC2S300E, Bank 6, 400E, 600E L#N_Y I I I/O, L XC2S200E, 400E, 600E ...

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... R FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E) Pad Name LVDS Async. Output Function Bank Pin Option M0 - AA1 - M2 - AB2 - I/O, L#N_Y 5 AA3 XC2S150E, 200E, 300E, 400E, 600E I/O, L#P_Y 5 AB3 XC2S150E, 200E, 300E, 400E, 600E I/O 5 AB4 - I/O 5 AA5 XC2S100E, 150E ...

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... Spartan-IIE FPGA Family: Pinout Tables FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E) Pad Name LVDS Async. Output Function Bank Pin Option I/O, VREF 5 V8 XC2S100E, Bank 5, 200E, 300E, L#N_Y 400E, 600E I/O, L#P_Y 5 W8 XC2S100E, 200E, 300E, 400E, 600E I/O, L#N_Y ...

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... R FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E) Pad Name LVDS Async. Output Function Bank Pin Option GCK0 AA12 - I/O (DLL), 4 Y12 - L#P I/O 4 W12 - I/O, L#N 4 V12 XC2S150E, 300E, 600E I/O, L#P 4 U12 XC2S150E, 300E, 600E I/O, L#N 4 AB13 XC2S300E, ...

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... Spartan-IIE FPGA Family: Pinout Tables FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E) Pad Name LVDS Async. Output Function Bank Pin Option I/O, L#N 4 AA16 XC2S150E, 200E, 400E I/O, L#P 4 Y16 XC2S150E, 200E, 400E I/O, L#N 4 W16 XC2S150E, 200E I/O, L#P ...

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... R FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E) Pad Name LVDS Async. Output Function Bank Pin Option I/O, L#N 3 V19 XC2S150E, 200E, 300E, 400E I/O, L#P 3 V20 XC2S150E, 200E, 300E, 400E I/O, L#N 3 V22 XC2S100E, 200E, 300E, 600E I/O, L#P 3 U22 ...

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... Spartan-IIE FPGA Family: Pinout Tables FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E) Pad Name LVDS Async. Output Function Bank Pin Option I/O 3 P20 - I/O, L#N 3 P18 XC2S150E, 200E, 300E, 400E I/O, L#P 3 P19 XC2S100E, 150E, 200E, 300E, 400E I/O, L#N ...

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... R FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E) Pad Name LVDS Async. Output Function Bank Pin Option I/O, L#P 2 L17 XC2S100E, 150E, 200E, 300E, 600E I/O, L#N 2 K22 XC2S100E, 150E, 300E, 400E I/O, L#P 2 K21 XC2S300E, 400E I/O 2 K20 - I/O (D3) ...

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... Spartan-IIE FPGA Family: Pinout Tables FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E) Pad Name LVDS Async. Output Function Bank Pin Option I/O, L#N 2 G21 XC2S200E, 400E, 600E I/O, L#P 2 G20 XC2S200E, 400E, 600E I/O, L#N 2 G19 XC2S150E, 300E I/O, L#P ...

Page 85

... R FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E) Pad Name LVDS Async. Output Function Bank Pin Option I/O 1 A20 All (WRITE), L#N_YY I/O 1 D18 - I/O 1 C18 - I/O, L#P 1 B19 XC2S200E, 300E, 400E, 600E I/O, L#N 1 A19 XC2S200E, 300E, 400E, 600E I/O, L#P ...

Page 86

... Spartan-IIE FPGA Family: Pinout Tables FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E) Pad Name LVDS Async. Output Function Bank Pin Option I/O, L#N 1 A15 XC2S100E, 200E, 300E, 400E, 600E I/O 1 E14 - I/O, L#P 1 D14 XC2S150E, 300E, 400E, 600E I/O, L#N ...

Page 87

... R FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E) Pad Name LVDS Async. Output Function Bank Pin Option I/O 0 F11 - I/O, L#P 0 A10 XC2S300E, 600E I/O, L#N 0 B10 XC2S300E, 600E I/O 0 E11 - I/O, L#P 0 C10 XC2S200E, 300E, 400E, 600E I/O, VREF 0 D10 ...

Page 88

... Spartan-IIE FPGA Family: Pinout Tables FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E) Pad Name LVDS Async. Output Function Bank Pin Option I/ All L#P_YY I/O, VREF 0 B6 All Bank 0, L#N_YY I XC2S100E I/O, L XC2S100E I/ I/O, L XC2S100E, 200E, 300E, 400E, 600E ...

Page 89

... Not Connected Pins (2) ( Notes: 1. VCCINT connections in XC2S400E and XC2S600E. No Connects (no internal connection) in XC2S100E, XC2S150E, XC2S200E, and XC2S300E. 2. GND connections in XC2S400E and XC2S600E. No Connects (no internal connection) in XC2S100E, XC2S150E, XC2S200E, and XC2S300E FG676 Pinouts (XC2S400E, XC2S600E) Pad Name Function Bank TMS - I/O 7 I/O, L204P ...

Page 90

... Spartan-IIE FPGA Family: Pinout Tables FG676 Pinouts (XC2S400E, XC2S600E) (Continued) Pad Name Function Bank I/O, L201P 7 I/O, L201N 7 I/O, VREF Bank 7, 7 L200P I/O, L200N 7 I/O, L199P 7 I/O, L199N 7 I/O, L198P 7 I/O, L198N 7 I/O, L197P 7 I/O, L197N 7 I/O, VREF Bank 7, 7 L196P_YY ...

Page 91

... R FG676 Pinouts (XC2S400E, XC2S600E) (Continued) Pad Name Function Bank I/O, L188P 7 I/O, L188N 7 I/O, L187P 7 I/O, L187N 7 I/O 7 I/O, L186P 7 I/O, L186N 7 I/O 7 I/O, L185P 7 I/O, L185N 7 I/O, VREF Bank 7, 7 L184P_YY I/O, L184N_YY 7 I/O 7 I/O, L183P_YY 7 I/O, L183N_YY 7 I/O 7 I/O, L182P ...

Page 92

... Spartan-IIE FPGA Family: Pinout Tables FG676 Pinouts (XC2S400E, XC2S600E) (Continued) Pad Name Function Bank I/O, VREF Bank 6, 6 L176N I/O, L175P 6 I/O, L175N 6 I/O 6 I/O, L174P_YY 6 I/O, L174N_YY 6 I/O 6 I/O, L173P_YY 6 I/O, VREF Bank 6, 6 L173N_YY I/O, L172P 6 I/O, L172N 6 I/O ...

Page 93

... R FG676 Pinouts (XC2S400E, XC2S600E) (Continued) Pad Name Function Bank I/O, L164N 6 I/O, L163P 6 I/O, L163N 6 I/O 6 I/O, L162P_YY 6 I/O, L162N_YY 6 I/O 6 I/O, L161P_YY 6 I/O, VREF Bank 6, 6 L161N_YY I/O 6 I/O, L160P_YY 6 I/O, L160N_YY 6 I/O, L159P 6 I/O, L159N 6 I/O 6 I/O, L158P 6 I/O, VREF Bank 6, ...

Page 94

... Spartan-IIE FPGA Family: Pinout Tables FG676 Pinouts (XC2S400E, XC2S600E) (Continued) Pad Name Function Bank I/O 5 AC5 I/O, L152N 5 I/O, L152P 5 I/O, L151N 5 I/O, L151P 5 I/O, L150N 5 I/O, L150P 5 I/O, L149N_YY 5 AC6 I/O, L149P_YY 5 AD6 I/O, VREF Bank 5, 5 L148N_YY I/O, L148P_YY ...

Page 95

... R FG676 Pinouts (XC2S400E, XC2S600E) (Continued) Pad Name Function Bank I/O, L138P_YY 5 I/O, L137N_YY 5 AB10 I/O, L137P_YY 5 AC10 I/O 5 AD10 I/O, L136N 5 AE10 I/O, L136P 5 AF10 I/O 5 AD11 I/O, L135N_YY 5 W11 I/O, L135P_YY 5 I/O, L134N_YY 5 AA11 I/O, L134P_YY 5 AB11 I/O 5 I/O, L133N ...

Page 96

... Spartan-IIE FPGA Family: Pinout Tables FG676 Pinouts (XC2S400E, XC2S600E) (Continued) Pad Name Function Bank GCK0 AF14 I/O (DLL), L126P 4 AE14 I/O 4 AD14 I/O, L125N 4 AC14 I/O, L125P 4 AB14 I/O 4 AC15 I/O, L124N 4 AA14 I/O, VREF Bank 4, 4 L124P I/O, L123N 4 AF15 ...

Page 97

... R FG676 Pinouts (XC2S400E, XC2S600E) (Continued) Pad Name Function Bank I/O 4 AC18 I/O, VREF Bank 4, 4 AB18 L114N I/O, L114P 4 AA18 I/O, L113N 4 I/O, L113P 4 W18 I/O 4 AB19 I/O, L112N 4 AF19 I/O, L112P 4 AE19 I/O, L111N 4 AA19 I/O, L111P 4 I/O 4 AF20 I/O, L110N ...

Page 98

... Spartan-IIE FPGA Family: Pinout Tables FG676 Pinouts (XC2S400E, XC2S600E) (Continued) Pad Name Function Bank DONE 3 AE26 PROGRAM - AC24 I/O (INIT), L101N_YY 3 AD25 I/O (D7), L101P_YY 3 AD26 I/O, L100N 3 AC25 I/O, L100P 3 AC26 I/O, L99N 3 AB22 I/O, L99P 3 AB23 I/O, L98N_YY 3 AB25 I/O, L98P_YY ...

Page 99

... R FG676 Pinouts (XC2S400E, XC2S600E) (Continued) Pad Name Function Bank I/O, L88P_YY 3 I/O 3 I/O, VREF Bank 3, 3 L87N_YY I/O (D6), L87P_YY 3 I/O (D5), L86N_YY 3 I/O, L86P_YY 3 I/O 3 I/O, L85N 3 I/O, L85P 3 I/O 3 I/O, L84N 3 I/O, L84P 3 I/O, L83N 3 I/O, L83P 3 I/O 3 I/O, L82N 3 I/O, L82P ...

Page 100

... Spartan-IIE FPGA Family: Pinout Tables FG676 Pinouts (XC2S400E, XC2S600E) (Continued) Pad Name Function Bank I/O 3 I/O (TRDY) 3 I/O (IRDY), L75N_YY 2 I/O, L75P_YY 2 I/O 2 I/O, L74N 2 I/O, L74P 2 I/O 2 M23 I/O, L73N 2 I/O, VREF Bank 2, 2 L73P I/O, L72N 2 M26 I/O, L72P ...

Page 101

... R FG676 Pinouts (XC2S400E, XC2S600E) (Continued) Pad Name Function Bank I/O, L64N_YY 2 I/O (D2), L64P_YY 2 I/O (D1) 2 I/O, VREF Bank 2, 2 L63N_YY I/O, L63P_YY 2 I/O, L62N_YY 2 I/O, L62P_YY 2 I/O 2 I/O, L61N 2 I/O, L61P 2 I/O, L60N 2 I/O, L60P 2 I/O 2 I/O, L59N_YY 2 I/O, L59P_YY 2 I/O ...

Page 102

... Spartan-IIE FPGA Family: Pinout Tables FG676 Pinouts (XC2S400E, XC2S600E) (Continued) Pad Name Function Bank I/O, L51N 2 I/O, L51P 2 I/O (DIN, D0), 2 L50N_YY I/O (DOUT, BUSY), 2 L50P_YY CCLK 2 TDO 2 TDI - I/O (CS), L49P_YY 1 I/O (WRITE), L49N_YY 1 I/O, L48P 1 I/O, L48N 1 I/O, L47P 1 I/O, L47N ...

Page 103

... R FG676 Pinouts (XC2S400E, XC2S600E) (Continued) Pad Name Function Bank I/O, L39N 1 I/O, L38P 1 I/O, L38N 1 I/O, L37P_YY 1 I/O, L37N_YY 1 I/O, L36P_YY 1 I/O, L36N_YY 1 I/O, VREF Bank 1, 1 L35P_YY I/O, L35N_YY 1 I/O, L34P_YY 1 I/O, L34N_YY 1 I/O 1 I/O, L33P 1 I/O, L33N 1 I/O 1 I/O, L32P_YY ...

Page 104

... Spartan-IIE FPGA Family: Pinout Tables FG676 Pinouts (XC2S400E, XC2S600E) (Continued) Pad Name Function Bank I/O, VREF Bank 1, 1 L25P I/O, L25N 1 I/O 1 I/O, L24P 1 I/O, L24N 1 I/O 1 I/O (DLL), L23P 1 GCK2 GCK3 I/O (DLL), L23N 0 I/O 0 I/O, L22P_YY 0 I/O, L22N_YY 0 I/O, L21P ...

Page 105

... R FG676 Pinouts (XC2S400E, XC2S600E) (Continued) Pad Name Function Bank I/O, L14N_YY 0 I/O 0 I/O, L13P 0 I/O, L13N 0 I/O 0 I/O, L12P_YY 0 I/O, L12N_YY 0 I/O 0 I/O, VREF Bank 0, 0 L11P I/O, L11N 0 I/O, L10P 0 I/O, L10N 0 I/O 0 I/O, L9P 0 I/O, L9N 0 I/O, L8P 0 I/O, L8N ...

Page 106

... Spartan-IIE FPGA Family: Pinout Tables FG676 Pinouts (XC2S400E, XC2S600E) (Continued) Pad Name Function Bank I/O, L2N_YY 0 I/O, L1P_YY 0 I/O, L1N_YY 0 I/O, L0P 0 I/O, L0N 0 I/O 0 TCK - FG676 Differential Clock Pins Clock Bank GCK0 4 GCK1 5 GCK2 1 GCK3 0 Additional FG676 Package Pins VCCINT Pins ...

Page 107

R Additional FG676 Package Pins (Continued) GND Pins A1 A26 C24 D4 H4 H23 L14 L15 M14 M15 N14 N15 P15 P16 R15 R16 T15 T16 AA17 AC4 AD15 AD24 Not Connected Pins (XC2S400E Only) A12 A16 C11 C25 E7 ...

Page 108

... Corrected differential pin pair designations. 2.0 11/18/02 Added XC2S400E and XC2S600E and FG676. Removed L37 designation from FT256 pinouts. Minor corrections and clarifications to pinout definitions. Removed Preliminary designation. 2.1 02/14/03 Added differential pairs table on Clarified that XC2S50E has two VREF pins per bank. ...