MT90870AG Zarlink, MT90870AG Datasheet - Page 59

• Manufacturer Part Number: MT90870AG
• Description: Switch Fabric 12K x 12K/8K x 4K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90870AG

• Package: 272BGA
• Number Of Ports: 32
• Fabric Size: 12K x 12K|8K x 4K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 2.048|4.096|8.192|16.384 Mbps
• Operating Supply Voltage: 1.8|3.3 V

13.6
Address 0043h to 0062h
Thirty-two Backplane input channel delay registers (BCDR0 to BCDR31) allow users to program the input channel
delay for the Backplane input data streams BSTi0-31. The possible adjustment is 511 channels and the BCDR0 to
BCDR31 registers are configured as follows:
13.6.1
These nine bits define the delay, in channel numbers, the serial interface receiver takes to store the channel data
from the Backplane stream input pins. The input channel delay can be set to 511 (32 Mb/s streams), 255 (16 Mb/s
streams), 127 (8 Mb/s streams), 63 (4 Mb/s streams) or 31 (2 Mb/s streams) from the frame boundary.
(where n = 0 to 31 for non-32Mb/s
mode, n = 0 to 15 for 32Mb/s
Data Rate
Backplane Input Channel Delay Registers (BCDR0 to BCDR31)
4 1/4
4 1/2
4 3/4
5 1/4
5 1/2
5 3/4
6 1/4
6 1/2
6 3/4
7 1/4
7 1/2
7 3/4
BCDRn Bit
Backplane Channel Delay Bits 8-0 (BCDn8 - BCDn0)
4
5
6
7
mode)
15-9
8-0
Table 22 - Local Input Bit Delay Programming Table (continued)
Table 23 - Backplane Channel Delay Register (BCDRn) Bits
LID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Reserved
BCD(8:0)
Name
Zarlink Semiconductor Inc.
LID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MT90870
Reset
0
0
Corresponding Delay Bits
59
Reserved
Backplane Channel Delay Register
The binary value of these bits refers to the channel
delay value for the Backplane input stream
LID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Description
LID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Data Sheet
LID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1