72841L15PF Integrated Device Technology (Idt), 72841L15PF Datasheet - Page 15

• Manufacturer Part Number: 72841L15PF
• Description: FIFO Mem Sync Quad Depth/Width Bi-Dir 4K x 9 x 2 64-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72841L15PF

• Package: 64TQFP
• Configuration: Quad
• Bus Directional: Bi-Directional
• Density: 72 Kb
• Organization: 4Kx9x2
• Data Bus Width: 9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

TWO PRIORITY DATA BUFFER
CONFIGURATION
72851 can be used to prioritize two different types of data shared on a system
bus. When writing from the bus to the FIFO, control logic sorts the intermixed
BIDIRECTIONAL CONFIGURATION
be used to buffer data flow in two directions. In the example that follows, a
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
The two FIFOs contained in the IDT72801/72811/72821/72831/72841/
The two FIFOs of the IDT72801/72811/72821/72831/72841/72851 can
Processor
Processor
RAM
RAM
Address
Control
Address
Control
Clock
Clock
Data
Data
9
9
9
9
Figure 17. Block Diagram of Bidirectional Configuration
Figure 16. Block Diagram of Two Priority Configuration
V
CC
9
V
CC
9
9
9
WENA2 RENA2
WCLKA
WENA1
RCLKB
RENB1
OEB
RENB2
RAM ARRAY A
DA0-DA8
RAM ARRAY B
QB0-QB8
72801
72811
72821
72831
72841
72851
WCLKA
WENA1
WENA2 RENA2
D
WCLKB
WENB1
D
WENB2 RENB2
IDT
RAM ARRAY B
QA0-QA8
RAM ARRAY A
DB0-DB8
A0
B0
V
WENB1
WCLKB
WENB2
RCLKA
RENA1
-D
-D
CC
TM
A8
B8
72801
72811
72821
72831
72841
72851
OEA
IDT
15
Q
Q
RCLKB
RENB1
RCLKA
A0
B0
data according to type, sending one kind to FIFO A and the other kind to FIFO
B. Then, at the outputs, each data type is transferred to its appropriate
destination. Additional IDT72801/72811/72821/72831/72841/72851s permit
more than two priority levels. Priority buffering is particularly useful in network
applications.
processor can write data to a peripheral controller via FIFO A, and, in turn,
the peripheral controller can write the processor via FIFO B.
RENA
OEB2
OEA
-Q
-Q
A8
9
B8
9
9
9
Clock
Clock
Data
Data
9
Voice Processing
Image Processing
Card
DMA Clock
Control
Data
Address
Card
Peripheral
Controller
Control
Control
Address
Address
COMMERCIAL AND INDUSTRIAL
3034 drw 18
I/O Data
TEMPERATURE RANGES
3034 drw 17
I/O Data
I/O Data
JANUARY 13, 2009