72841L15PF Integrated Device Technology (Idt), 72841L15PF Datasheet - Page 6

• Manufacturer Part Number: 72841L15PF
• Description: FIFO Mem Sync Quad Depth/Width Bi-Dir 4K x 9 x 2 64-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72841L15PF

• Package: 64TQFP
• Configuration: Quad
• Bus Directional: Bi-Directional
• Density: 72 Kb
• Organization: 4Kx9x2
• Data Bus Width: 9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

SIGNAL DESCRIPTIONS
explains the interaction of input and output signals for FIFO A. The correspond-
ing signal names for FIFO B are provided in parentheses.
INPUTS:
for memory array A. DB0 - DB8 are the nine data inputs for memory array B.
CONTROLS:
(RSB) input is taken to a LOW state. During Reset, the internal read and write
pointers associated with the FIFO are set to the first location. A Reset is required
after power-up before a write operation can take place. The Full Flag FFA (FFB)
and Programmable Almost-Full flag PAFA (PAFB) will be reset to HIGH after
tRSF. The Empty Flag EFA (EFB) and Programmable Almost-Empty flag PAEA
(PAEB) will be reset to LOW after tRSF. During Reset, the output register is
initialized to all zeros and the offset registers are initialized to their default values.
initiated on the LOW-to-HIGH transition of WCLKA (WCLKB). Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of
WCLKA (WCLKB). The Full Flag FFA (FFB) and Programmable Almost-Full
flag PAFA (PAFB) are synchronized with respect to the LOW-to-HIGH transition
of the Write Clock WCLKA (WCLKB).
programmable flags, WENA1 (WENB1) is the only enable control pin. In this
configuration, when WENA1 (WENB1) is LOW, data can be loaded into the input
register of RAM Array A (B) on the LOW-to-HIGH transition of every Write Clock
WCLKA (WCLKB). Data is stored in Array A (B) sequentially and independently
of any ongoing read operation.
the previous data and no new data is allowed to be loaded into the register.
expansion. See Write Enable 2 paragraph below for operation in this
configuration.
operations. Upon the completion of a valid read cycle, the FFA (FFB) will go HIGH
after t
A (B) is full.
the LOW-to-HIGH transition of RCLKA (RCLKB). The Empty Flag EFA (EFB)
and Programmable Almost-Empty Flag PAEA (PAEB) are synchronized with
respect to the LOW-to-HIGH transition of RCLKA (RCLKB).
Enables RENA1, RENA2 (RENB1, RENB2) are LOW, data is read from Array
A (B) to the output register on the LOW-to-HIGH transition of the Read Clock
RCLKA (RCLKB).
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
FIFO A and FIFO B are identical in every respect. The following description
Data In (DA0 – DA8, DB0 – DB8)
Reset
Write Clock (WCLKA, WCLKB) — A write cycle to Array A (B) is
The Write and Read Clocks can be asynchronous or coincident.
Write Enable 1 (WENA1, WENB1) — If FIFO A (B) is configured for
In this configuration, when WENA1 (WENB1) is HIGH, the input register holds
If the FIFO is configured to have two write enables, which allows for depth
To prevent data overflow, FFA (FFB) will go LOW, inhibiting further write
Read Clock (RCLKA, RCLKB) — Data can be read from Array A (B) on
The Write and Read Clocks can be asynchronous or coincident.
Read Enables (RENA1, RENA2, RENB1, RENB2) — When both Read
WFF
, allowing a valid write to begin. WENA1 (WENB1) is ignored when FIFO
(
RSA, RSB) — Reset of FIFO A (B) is accomplished whenever RSA
—
DA0 - DA8 are the nine data inputs
TM
6
associated with FIFO A (B) is HIGH, the output register holds the previous data
and no new data is allowed to be loaded into the register.
will go LOW, inhibiting further read operations. Once a valid write operation has
been accomplished, EFA (EFB) will go HIGH after tREF and a valid read can
begin. The Read Enables RENA1, RENA2 (RENB1, RENB2) are ignored when
FIFO A (B) is empty.
(LOW), the parallel output buffers of FIFO A (B) receive data from their respective
output register. When Output Enable OEA (OEB) is disabled (HIGH), the QA
(QB) output data bus is in a high-impedance state.
purpose pin. FIFO A (B) is configured at Reset to have programmable flags
or to have two write enables, which allows depth expansion. If WENA2/LDA
(WENB2/LDB) is set HIGH at Reset RSA = LOW (RSB = LOW), this pin operates
as a second write enable pin.
1 WENA1 (WENB1) is LOW and WENA2/LDA (WENB2/LDB) is HIGH, data can be
loaded into the input register and RAM array on the LOW-to-HIGH transition
of every Write Clock WCLKA (WCLKB). Data is stored in the array sequentially
and independently of any ongoing read operation.
(WENB2/LDB) is LOW, the input register of Array A holds the previous data and
no new data is allowed to be loaded into the register.
further write operations. Upon the completion of a valid read cycle, FFA (FFB)
will go HIGH after tWFF, allowing a valid write to begin. WENA1, (WENB1) and
WENA2/LDA (WENB2/LDB) are ignored when the FIFO is full.
LDA (WENB2/LDB) is set LOW at Reset RSA = LOW (RSB = LOW). Each FIFO
contains four 8-bit offset registers which can be loaded with data on the inputs,
or read on the outputs. See Figure 3 for details of the size of the registers and
the default values.
(WENB1) and WENA2/LDA (WENB2/LDB) are set LOW, data on the DA (DB)
inputs are written into the Empty (Least Significant Bit) Offset register on the first
LOW-to-HIGH transition of the WCLKA (WCLKB). Data are written into the
Empty (Most Significant Bit) Offset register on the second LOW-to-HIGH
transition of WCLKA (WCLKB), into the Full (Least Significant Bit) Offset register
on the third transition, and into the Full (Most Significant Bit) Offset register on
the fourth transition. The fifth transition of WCLKA (WCLKB) again writes to the
Empty (Least Significant Bit) Offset register.
or two offset registers can be written and then by bringing LDA (LDB) HIGH, FIFO
A (B) is returned to normal read/write operation. When LDA (LDB) is set LOW,
and WENA1 (WENB1) is LOW, the next offset register in sequence is written.
WENA2/LDA (WENB2/LDB) is set LOW and both Read Enables RENA1, RENA2
(RENB1, RENB2) are set LOW. Data can be read on the LOW-to-HIGH transition
of the Read Clock RCLKA (RCLKB).
When either of the two Read Enable RENA1, RENA2 (RENB1, RENB2)
When all the data has been read from FIFO A (B), the Empty Flag EFA (EFB)
Output Enable (OEA, OEB) — When Output Enable OEA (OEB) is enabled
Write Enable 2/Load (WENA2/LDA, WENB2/LDB) — This is a dual-
If FIFO A (B) is configured to have two write enables, when Write Enable
In this configuration, when WENA1 (WENB1) is HIGH and/or WENA2/LDA
To prevent data overflow, the Full Flag FFA (FFB) will go LOW, inhibiting
FIFO A (B) is configured to have programmable flags when the WENA2/
If FIFO A (B) is configured to have programmable flags, when the WENA1
However, writing all offset registers does not have to occur at one time. One
The contents of the offset registers can be read on the QA (QB) outputs when
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JANUARY 13, 2009