CS5102A-JL Cirrus Logic Inc, CS5102A-JL Datasheet - Page 15

• Manufacturer Part Number: CS5102A-JL
• Description: ADC Single SAR 20KSPS 16-Bit Serial 28-Pin PLCC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5102A-JL

• Package: 28PLCC
• Resolution: 16 Bit
• Sampling Rate: 20 KSPS
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 2
• Digital Interface Type: Serial
• Input Type: Voltage
• Signal To Noise Ratio: 90(Typ) dB
• Polarity Of Input Voltage: Unipolar|Bipolar

clock yields a maximum throughput of 20 kHz in
a single channel configuration.
Asynchronous Sampling Considerations
When HOLD goes low, the analog sample is cap-
tured immediately. The HOLD signal is latched
by the next falling edge of CLKIN, and conver-
sion then starts on the subsequent rising edge. If
HOLD is asynchronous to CLKIN, then there
will be a 1.5 CLKIN cycle uncertainty as to when
conversion starts. Considering the CS5101A with an
8 MHz CLKIN, with a 100 kHz HOLD signal, then
this 1.5 CLKIN uncertainty will result in a 1.5
CLKIN period possible reduction in fine charge time
for the next conversion.
DS45F2
>(VREF-1.5 LSB) FFFF
VREF/2-0.5 LSB 8000
Unipolar Input
VREF-1.5 LSB
<(+0.5 LSB)
+0.5 LSB
Voltage
Table 1. Output Coding
CLKIN
CRS/FIN
Internal
Status
TRK1 or
TRK2
HOLD
Binary
Offset
FFFE
FFFF
7FFF
0001
0000
0000
Complement
** Applies to 5102A
* Applies to 5101A
Conv.
Two’s
7FFE
FFFF
7FFF
7FFF
0000
8001
8000
8000
Figure 2. Coarse-Charge/Fine-Charge Control
Coarse
<(-VREF+0.5 LSB)
>(VREF-1.5 LSB)
-VREF+0.5 LSB
VREF-1.5 LSB
2 clk
Bipolar Input
-0.5 LSB
Voltage
Min: 750 ns*
6 clk
Fine Chg.
3.75 s**
Min: 1.125 s*
5.625 s**
Coarse
This reduced fine charge time will be less than
the minimum specification. If the CLKIN fre-
quency is increased slightly (for example, to
8.192 MHz) then sufficient fine charge time will
always occur. The maximum frequency for
CLKIN is specified at 9.216 MHz; it is recom-
mended that for asynchronous operation at
100 kHz, CLKIN should be between 8.192 MHz
and 9.216 MHz.
Analog Input Range/Coding Format
The reference voltage directly defines the input
voltage range in both the unipolar and bipolar
configurations. In the unipolar configuration
(BP/UP low), the first code transition occurs 0.5
LSB above AGND, and the final code transition
occurs 1.5 LSB’s below VREF. In the bipolar
configuration (BP/UP high), the first code transi-
tion occurs 0.5 LSB above -VREF and the last
transition occurs 1.5 LSB’s below +VREF.
The CS5101A and CS5102A can output data in
either 2’s complement, or binary format. If the
CODE pin is high, the output is in 2’s comple-
ment format with a range of -32,768 to +32,767.
If the CODE pin is low, the output is in binary
format with a range of 0 to +65,535. See Table 1
for output coding.
Fine Chg.
CS5101A CS5102A
Conv.
15