M38517F8FP Renesas Electronics America, M38517F8FP Datasheet
M38517F8FP
Specifications of M38517F8FP
Related parts for M38517F8FP
M38517F8FP Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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... Power dissipation In high-speed mode ......................................................... 34 mW (at 8 MHz oscillation frequency power source voltage) In low-speed mode Except M38517F8FP/SP ................................................. 60 W M38517F8FP/SP ............................................................ 450 W (at 32 kHz oscillation frequency power source voltage) Operating temperature range .................................. –20 to 85°C APPLICATION Office automation equipment, FA equipment, Household products, Consumer electronics, etc ...
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Group (Built- more ROM) FUNCTIONAL BLOCK Fig.2 Functional block diagram Rev.1.01 Oct 15, 2003 page ...
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Group (Built- more ROM) Table 1 Pin description Pin Name Power source CNV CNV input Reference REF voltage input AV Analog power SS source input Reset input RESET ...
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Group (Built- more ROM) PART NUMBERING Product name Fig. 3 Part numbering Rev.1.01 Oct 15, 2003 page – ...
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Group (Built- more ROM) GROUP EXPANSION Renesas plans to expand the 3851 group (built- more ROM) as follows. Memory Type Support for mask ROM, One Time PROM, and flash memory ver- sions. Memory ...
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... Rev.1.01 Oct 15, 2003 page RAM size (bytes) Package ) 42P4B 640 42S1B-A 42P2R-A/E 3851 group (built- more ROM) M38514M6-XXXFP/SP M38514E6-XXXFP/SP M38514E6FP/SP M38514E6SS M38517M8-XXXFP/SP M38517F8FP/SP 3851 group (built- ROM) (UART or Clock-synchronized) – may IN OUT CIN COUT Remarks Mask ROM version One Time PROM version ...
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Group (Built- more ROM) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3851 group uses the standard 740 Family instruction set. Re- fer to the table of 740 Family addressing modes and machine instructions or the 740 ...
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Group (Built- more ROM ( ...
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Group (Built- more ROM) [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide ...
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Group (Built- more ROM) [CPU Mode Register (CPUM)] 003B The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B b 7 Fig. 7 Structure of CPU ...
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Group (Built- more ROM) MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and ...
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Group (Built- more ROM ...
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Group (Built- more ROM) I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can ...
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Group (Built- more ROM) (1) Port P0 0 Direction register Port latch Data bus Serial I/O2 input (3) Port P-channel output disable bit 2 CLK2 Serial I/O2 synchronous clock selection bit Serial ...
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Group (Built- more ROM) (9) Port C-BUS interface enable bit SDA/SCL pin selection bit Direction register Port latch Data bus SCL output (11) Port P2 5 P-channel output disable bit Serial I/O1 ...
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Group (Built- more ROM) (17) Port ...
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Group (Built- more ROM) INTERRUPTS Interrupts occur seven external, nine internal, and one soft- ware. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt ...
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Group (Built- more ROM) Table 8 Interrupt vector addresses and priority Vector Addresses (Note 1) Interrupt Source Priority High 1 FFFD Reset (Note 2) INT 0 2 FFFB 3 SCL, SDA FFF9 INT 1 4 FFF7 ...
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Group (Built- more ROM ...
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Group (Built- more ROM) TIMERS The 3851 group (built- more ROM) has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given ...
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Group (Built- more ROM ...
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Group (Built- more ROM) SERIAL I/O SERIAL I/O1 Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer is also provided for baud rate generation ...
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Group (Built- more ROM) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “0”. ...
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Group (Built- more ROM) Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output Receive buffer read signal ST Serial input Notes 1: Error flag detection ...
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Group (Built- more ROM (SIOSTS : address 0019 ...
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Group (Built- more ROM) SERIAL I/O2 The serial I/O2 can be operated only as the clock synchronous type synchronous clock for serial transfer, either internal clock or external clock can be selected by the ...
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Group (Built- more ROM) X CIN Main clock division ratio selection bits (Note “0” RDY2 “1” S output enable bit RDY2 P0 latch 2 “0” CLK2 ...
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Group (Built- more ROM Fig output operation CMP2 Rev.1.01 Oct 15, 2003 page 28 of ...
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Group (Built- more ROM) 2 MULTI-MASTER I C-BUS INTERFACE 2 The multi-master I C-BUS interface is a serial communications cir- 2 cuit, conforming to the Philips I C-BUS data transfer format. This interface, offering both arbitration ...
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Group (Built- more ROM Data Shift Register (S0)] 002B 2 The I C data shift register (S0 : address 002B register to store receive data and write transmit data. When transmit data is ...
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Group (Built- more ROM Clock Control Register (S2)] 002F 2 The I C clock control register (address 002F control, SCL mode and SCL frequency. •Bits SCL frequency control bits (CCR0–CCR4) ...
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Group (Built- more ROM Control Register (S1D)] 002E 2 The I C control register (address 002E cation format. •Bits Bit counter (BC0–BC2) These bits decide the number of bits for ...
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Group (Built- more ROM Status Register (S1)] 002D 2 The I C status register (address 002D terface status. The low-order 4 bits are read-only bits and the high-order 4 bits can be read ...
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Group (Built- more ROM) •Bit 6: Communication mode specification bit (transfer direc- tion specification bit: TRX) This bit decides a direction of transfer for data communication. When this bit is “0”, the reception mode is selected ...
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Group (Built- more ROM) START Condition Generating Method When writing “1” to the MST, TRX, and BB bits of the I register (address 002D ) at the same time after writing the slave 16 2 address ...
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Group (Built- more ROM START/STOP Condition Control Register (S2D)] 0030 16 2 The I C START/STOP condition control register (address 0030 controls START/STOP condition detection. •Bits START/STOP condition set bit ...
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Group (Built- more ROM ...
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Group (Built- more ROM) Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. (1) Set ...
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Group (Built- more ROM) Precautions when using multi-master I BUS interface (1) Read-modify-write instruction The precautions when the read-modify-write instruction such as SEB, CLB etc. is executed for each register of the multi-master 2 I C-BUS ...
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Group (Built- more ROM) PULSE WIDTH MODULATION (PWM) The 3851 group (built- more ROM) has a PWM func- tion with an 8-bit resolution, based on a signal that is the clock input X ...
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Group (Built- more ROM ...
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Group (Built- more ROM) A-D CONVERTER [A-D Conversion Registers (ADL, ADH)] 0035 , 0036 16 16 The A-D conversion registers are read-only registers that store the result of an A-D conversion. Do not read these registers ...
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Group (Built- more ROM) WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). The ...
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Group (Built- more ROM) RESET CIRCUIT To reset the microcomputer, RESET pin must be held at an “L” level for 20 cycles or more Then the RESET pin is returned ...
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Group (Built- more ROM ...
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Group (Built- more ROM) CLOCK GENERATING CIRCUIT The 3851 group (built- more ROM) has two built-in os- cillation circuits: main clock OUT clock X -X oscillation circuit. An oscillation circuit ...
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Group (Built- more ROM) Notes on middle-speed mode automatic switch set bit When the middle-speed mode automatic switch set bit is set to “1” while operating in the low-speed mode, by detecting the rising/fall- ing edge ...
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Group (Built- more ROM ...
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Group (Built- more ROM) FLASH MEMORY MODE The M38517F8 (flash memory version) has an internal new DINOR (DIvided bit line NOR) flash memory that can be rewritten with a single power source when V CC when ...
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Group (Built- more ROM) (1) CPU Rewrite Mode In CPU rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the Central Process- ing Unit (CPU). In CPU rewrite ...
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Group (Built- more ROM) Outline Performance (CPU Rewrite Mode) CPU rewrite mode is usable in the single-chip or Boot mode. The only User ROM area can be rewritten in CPU rewrite mode. In CPU rewrite mode, ...
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Group (Built- more ROM) Notes 1: When starting the MCU in the single-chip mode, supply 4 5 the CNVss pin until checking the CPU rewrite mode entry flag. 2: Set bits 6, ...
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Group (Built- more ROM) Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the internal ...
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Group (Built- more ROM) Software Commands (CPU Rewrite Mode) Table 16 lists the software commands. After setting the CPU Rewrite Mode Select Bit of the flash memory control register to “1”, execute a software command to ...
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Group (Built- more ROM) Erase All Blocks Command (20 / writing the command code “20 ” in the first bus cycle and the 16 confirmation command code “20 ” in the second bus cycle ...
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Group (Built- more ROM) Status Register (SRD) The status register shows the operating status of the flash memory and whether erase operations and programs ended suc- cessfully or in error. It can be read in the ...
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Group (Built- more ROM) Full Status Check By performing full status check possible to know the execu- tion results of erase and program operations. Figure 62 shows a Read status register YES SR4 = ...
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Group (Built- more ROM) Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use ...
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Group (Built- more ROM) ID Code Check Function (in Standard serial I/O mode) Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from ...
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Group (Built- more ROM) (2) Parallel I/O Mode Parallel I/O mode is the mode which parallel output and input soft- ware command, address, and data required for the operations (read, program, erase, etc built-in ...
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Group (Built- more ROM) (3) Standard serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, pro- gram, erase, etc.) the internal flash memory. This ...
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Group (Built- more ROM) Table 18 Description of pin function (Standard Serial I/O Mode) Pin Name V ,V Power input CC SS CNV CNV SS SS Reset input RESET X Clock input IN X Clock output ...
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Group (Built- more ROM) P4 /INT /INT /CNTR 0 B USY P2 /CNTR CLK1 P2 6 TxD P2 RxD ...
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Group (Built- more ROM) Software Commands (Standard Serial I/O Mode) Table 19 lists software commands. In standard serial I/O mode, erase, program and read are controlled by transferring software Table 19 Software commands (Standard serial I/O ...
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Group (Built- more ROM) Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. S CLK1 ...
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Group (Built- more ROM) Clear Status Register Command This command clears the bits (SR4, SR5) which are set when the status register operation ends in error. When the “50 code is sent with the 1st byte, ...
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Group (Built- more ROM) Erase All Blocks Command This command erases the contents of all blocks. Execute the erase all blocks command as explained here following. (1) Transfer the “A7 ” command code with the 1st ...
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Group (Built- more ROM) Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the “FA ” command code with the 1st byte. 16 ...
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Group (Built- more ROM) Version Information Output Command This command outputs the version information of the control pro- gram stored in the Boot ROM area. Execute the version information output command as explained here following. S ...
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Group (Built- more ROM) ID Check This command checks the ID code. Execute the boot ID check command as explained here following. S CLK1 F5 RxD TxD S (BUSY) RDY1 Fig. 73 Timing for ID check ...
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Group (Built- more ROM) Status Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be ...
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Group (Built- more ROM) Status Register 1 (SRD1) The status register 1 indicates the status of serial communica- tions, results from ID checks and results from check sum comparisons. It can be read after the status ...
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Group (Built- more ROM) Full Status Check Results from executed erase and program operations can be known by running a full status check. Figure 75 shows a flowchart of the full status check and explains how ...
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Group (Built- more ROM) Example Circuit Application for Standard Serial I/O Mode Figure 76 shows a circuit application for the standard serial I/O mode. Control pins will vary according to a programmer, therefore see a programmer ...
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Group (Built- more ROM) Flash memory Electrical characteristics Table 22 Absolute maximum ratings Symbol Parameter V Power source voltage CC Input voltage P0 – – REF V Input voltage P2 ...
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Group (Built- more ROM) NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. Af- ter a ...
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Group (Built- more ROM) Electric Characteristic Differences Among Mask ROM, Flash Memory, and One Time PROM Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation among mask ROM, flash memory, ...
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Group (Built- more ROM) Electrical characteristics Absolute maximum ratings Table 25 Absolute maximum ratings Symbol Parameter V Power source voltage CC Input voltage P0 – – REF V Input voltage ...
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Group (Built- more ROM) Recommended operating conditions Table 26 Recommended operating conditions ( 2 – °C, unless otherwise noted Symbol V Power source voltage CC ...
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Group (Built- more ROM) Table 27 Recommended operating conditions ( 2 – °C, unless otherwise noted) CC Symbol I “H” peak output current OH(peak) I “L” peak ...
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Group (Built- more ROM) Table 29 Electrical characteristics ( 2 – °C, unless otherwise noted Symbol Parameter V –V Hysteresis ...
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... IN M38517F8FP/ 32.768 kHz CIN M38517F8FP/SP Except ) = stopped M38517F8FP/ 32.768 kHz (in WIT state) M38517F8FP/SP Except = M38517F8FP/ stopped 32.768 kHz CIN M38517F8FP/SP Except = M38517F8FP/ stopped 32.768 kHz (in WIT state) M38517F8FP/ MHz stopped CIN ) = 8 MHz (in WIT state stopped CIN ) = 8 MHz ° °C Limits Max ...
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Group (Built- more ROM) A-D converter characteristics Table 31 A-D converter characteristics (V = 2 Symbol Parameter – Resolution – Absolute accuracy (excluding ...
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Group (Built- more ROM) Timing requirements Table 32 Timing requirements ( 4 – °C, unless otherwise noted Symbol Reset input ...
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Group (Built- more ROM) Switching characteristics Table 34 Switching characteristics ( 4 – °C, unless otherwise noted Symbol t (S ...
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Group (Built- more ROM) 2 MULTI-MASTER I C-BUS BUS LINE CHARACTERISTICS 2 Table 36 Multi-master I C-BUS bus line characteristics Symbol Parameter t Bus free time BUF t Hold time for START condition HD;STA t Hold ...
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Group (Built- more ROM ...
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Group (Built- more ROM) PACKAGE OUTLINE 42P4B MMP EIAJ Package Code JEDEC Code SDIP42-P-600-1. SEATING PLANE 42P2R-A/E EIAJ Package Code JEDEC Code SSOP42-P-450-0. Detail G 1 Rev.1.01 Oct ...
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Group (Built- more ROM) 42S1B-A EIAJ Package Code JEDEC Code WDIP42-C-600-1. Rev.1.01 Oct 15, 2003 page Weight(g) – SEATING PLANE Metal seal 42pin 600mil DIP ...
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REVISION HISTORY Rev. Date Page 1.00 – First edition issued Jul. 26, 2002 1.01 •Mitsubishi, Mitsubishi Electric Corporation Oct. 15, 2003 • Fig.4 Memory expansion plan Under development M38517M8/F8 14-15 “SDA input”, “SCL input” “Serial I/O1 input” 15 ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...