LFXP3E-3QN208C Lattice, LFXP3E-3QN208C Datasheet - Page 30

• Manufacturer Part Number: LFXP3E-3QN208C
• Description: IC FPGA 3.1KLUTS 208PQFP
• Manufacturer: Lattice

Specifications of LFXP3E-3QN208C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-29 provides a pictorial representation of the different programming ports and modes available in the Lat-
ticeXP devices.
On power-up, the FPGA SRAM is ready to be configured with the sysCONFIG port active. The IEEE 1149.1 serial
mode can be activated any time after power-up by sending the appropriate command through the TAP port.
Leave Alone I/O
When using 1532 mode for non-volatile memory programming, users may specify I/Os as high, low, tristated or
held at current value. This provides excellent flexibility for implementing systems where reprogramming occurs on-
the-fly.
TransFR (Transparent Field Reconfiguration)
TransFR (TFR) is a unique Lattice technology that allows users to update their logic in the field without interrupting
system operation using a single ispVM command. See Lattice technical note #TN1087, Minimizing System Inter-
ruption During Configuration Using TransFR Technology, for details.
Security
The LatticeXP devices contain security bits that, when set, prevent the readback of the SRAM configuration and
non-volatile memory spaces. Once set, the only way to clear security bits is to erase the memory space.
For more information on device configuration, please see details of additional technical documentation at the end
of this data sheet.
Figure 2-29. ispXP Block Diagram
Internal Logic Analyzer Capability (ispTRACY)
All LatticeXP devices support an internal logic analyzer diagnostic feature. The diagnostic features provide capabil-
ities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace mem-
ory. This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at compile
time.
For more information on ispTRACY, please see information regarding additional technical documentation at the
end of this data sheet.
Oscillator
Every LatticeXP device has an internal CMOS oscillator which is used to derive a master serial clock for configura-
tion. The oscillator and the master serial clock run continuously in the configuration mode. The default value of the
Port
Mode
Memory Space
Program in seconds
Memory Space
ISP 1149.1 TAP Port
BACKGND
1532
Download in microseconds
2-27
Power-up
Refresh
sysCONFIG Peripherial Port
Memory Space
sysCONFIG
LatticeXP Family Data Sheet
SRAM
Configure in milliseconds
Architecture