NUC140LE3CN Nuvoton Technology Corporation of America, NUC140LE3CN Datasheet - Page 471

• Manufacturer Part Number: NUC140LE3CN
• Description: IC MCU 32BIT 128KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC140LE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.16.4.5 Continuous Scan Mode
In continuous scan mode, A/D conversion is performed sequentially on the specified channels
that enabled by CHEN bits in ADCHER register (maximum 8 channels for ADC). The operations
are as follows:
An example timing diagram for continuous scan on enabled channels (0, 2, 3 and 7) is shown as
below:
1.
2.
3.
4.
NuMicro™ NUC130/NUC140 Technical Reference Manual
When the ADST bit in ADCR is set to 1 by software or external trigger input, A/D
conversion starts on the channel with the lowest number.
When A/D conversion for each enabled channel is completed, the result of each enabled
channel is stored in the A/D data register corresponding to each enabled channel.
When A/D converter completes the conversions of all enabled channels sequentially, the
ADF bit (ADSR[0]) will be set to 1. If the ADC interrupt function is enabled, the ADC
interrupt occurs. The conversion of the enabled channel with the lowest number will start
again if software has not cleared the ADST bit.
As long as the ADST bit remains at 1, the step 2 ~ 3 will be repeated. When ADST is
cleared to 0, ADC controller will finish current conversion and the result of the lowest
enabled ADC channel will become unpredictable.
Figure 5-104 Continuous Scan on Enabled Channels Timing Diagram
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Publication Release Date: June 14, 2011
Revision V2.01