AD8186ARU

Manufacturer Part NumberAD8186ARU
DescriptionIC MULTIPLEXER TRPL 2X1 24TSSOP
ManufacturerAnalog Devices Inc
AD8186ARU datasheet
 

Specifications of AD8186ARU

Rohs StatusRoHS non-compliantFunctionMultiplexer
Circuit3 x 2:1On-state Resistance350 mOhm
Voltage Supply SourceSingle SupplyVoltage - Supply, Single/dual (±)3.5 V ~ 5.5 V
Current - Supply15mAOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case24-TSSOP (0.173", 4.40mm Width)
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AD8186/AD8187
AC-Coupled Inputs (DC Restore before Mux Input)
Using ac-coupled inputs presents an interesting challenge for video
systems operating from a single 5 V supply. In NTSC and PAL
video systems, 700 mV is the approximate difference between the
maximum signal voltage and black level. It is assumed that sync
has been stripped. However, given the two pathological cases
shown in Figure 7, a dynamic range of twice the maximum signal
swing is required if the inputs are to be ac-coupled. A possible
solution would be to use a dc restore circuit before the mux.
WHITE LINE WITH BLACK PIXEL
+700mV
V
AVG
V
AVG
V
REF
BLACK LINE WITH WHITE PIXEL
+5 V
V
SIGNAL
GND
Figure 7. Pathological Case for
Input Dynamic Range
Tolerance to Capacitive Load
Op amps are sensitive to reactive loads. A capacitive load at the
output appears in parallel with an effective resistance of R
(R
r
), where R
is the discrete resistive load, and r
L
O
L
loop output impedance, approximately 15 Ω for these muxes.
The load pole, at f
= 1/(2 R
C
LOAD
EFF
phase margin and therefore stability. The old workaround is to
place a small series resistance directly at the output to isolate the
load pole. While effective, this ruse also affects the dc and termina-
tion characteristics of a 75 Ω system. The AD8186 and AD8187
are built with a variable compensation scheme that senses the
output reactance and trades bandwidth for phase margin, ensuring
faster settling and lower overshoot at higher capacitive loads.
Secondary Supplies and Supply Bypassing
The high current output transistors are given their own supply
pins (Pins 15, 17, 19, and 21) to reduce supply noise on-chip
and to improve output isolation. Since these secondary, high
current supply pins are not connected on-chip to the primary
analog supplies (V
/V
, Pins 6, 7, 9, 11, 13, and 24), some
CC
EE
care should be taken to ensure that the supply bypass capacitors
are connected to the correct pins. At a minimum, the primary
supplies should be bypassed. Pin 6 and Pin 7 may be a convenient
place to accomplish this. Stacked power and ground planes could
be a convenient way to bypass the high current supply pins.
V
REF
–700mV
V
= V
+ V
INPUT
REF
SIGNAL
V
~ V
REF
AVG
V
IS A DC VOLTAGE
REF
SET BY THE RESISTORS
Figure 8. Detail of Primary and Secondary Supplies
Split-Supply Operation
Operating from split supplies (e.g., +3 V/–2 V or ± 2.5 V) simpli-
fies the selection of the V
=
EFF
voltage. In this case, it is convenient to tie V
is the open-
O
The logic inputs are level shifted internally to allow the digital
supplies and logic inputs to operate from 0 V and 5 V when
), can seriously degrade
L
powering the analog circuits from split supplies. The maximum
voltage difference between DV
(see Figure 9).
–14–
IN0A
1
D
2
GND
IN1A
3
V
4
REF
IN2A
5
V
MUX0
6
CC
0.1 F
V
7
EE
1 F
IN2B
MUX1
8
V
9
EE
IN1B
10
MUX2
V
11
EE
IN0B
12
voltage and load resistor termination
REF
REF
and V
must not exceed 8 V
CC
EE
SPLIT-SUPPLY OPERATION
ANALOG SUPPLIES
DIGITAL SUPPLIES
(+2.5)
DV
(+5)
CC
8V MAX
(0V)
D
(–2.5)
GND
Figure 9. Split-Supply Operation
V
24
CC
23
OE
22
SEL A/B
V
21
CC
OUT 0
20
V
19
EE
OUT 1
18
V
17
CC
OUT 2
16
15
V
EE
DV
14
CC
13
V
CC
to ground.
V
CC
V
EE
REV. A