NCP3218GMNR2G ON Semiconductor, NCP3218GMNR2G Datasheet - Page 17

• Manufacturer Part Number: NCP3218GMNR2G
• Description: IC CTLR CPU SYNC BUCK 7BIT 48QFN
• Manufacturer: ON Semiconductor
• Series: -r

Specifications of NCP3218GMNR2G

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 3.3 V ~ 22 V
• Number Of Outputs: 1
• Voltage - Output: 0.0125 V ~ 1.5 V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

make RSWFB for that phase larger (that is, RSWFB = 100 W
for the hottest phase and do not change it during balance
optimization). Increasing RSWFB to 150 W makes a
substantial increase in phase current. Increase each RSWFB
value by small amounts to achieve thermal balance starting
with the coolest phase.
RSWFB should be 100 W for all phases.
Voltage Control Mode
voltage mode control loop. The non−inverting input voltage
is set via the 7−bit VID DAC. The VID codes are listed in
Table 3. The non−inverting input voltage is offset by the
droop voltage as a function of current, commonly known as
active voltage positioning. The output of the error amplifier
is the COMP pin, which sets the termination voltage of the
internal PWM ramps.
location using R
output voltage at the remote sensing point. The main loop
compensation is incorporated in the feedback network
connected between the FB and COMP pins.
Power−Good Monitoring
via the CSREF pin. The PWRGD pin is an open−drain
output that can be pulled up through an external resistor to
a voltage rail; not necessarily the same VCC voltage rail that
is running the controller. A logic high level indicates that the
output voltage is within the voltage limits defined by a range
around the VID voltage setting. PWRGD goes low when the
output voltage is outside of this range.
range is defined to be 300 mV less than and 200 mV greater
than the actual VID DAC output voltage. For any DAC
voltage less than 300 mV, only the upper limit of the
To increase the current in any given phase, users should
If adjusting current balance between phases is not needed,
A high−gain bandwidth error amplifier is used for the
At the negative input, the FB pin is tied to the output sense
The power−good comparator monitors the output voltage
Following the IMVP−6.5 specification, the PWRGD
ADP3212
SWFB3
SWFB2
SWFB1
Figure 19. Current Balance Resistors
33
24
28
B
R
R
, a resistor for sensing and controlling the
SWFB3
SWFB1
R
SWFB2
VDC
VDC
Phase 3
Inductor
Phase 1
Inductor
VDC
Phase 2
Inductor
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PWRGD range is monitored. To prevent a false alarm, the
power−good circuit is masked during various system
transitions, including a VID change and entrance into or exit
out of deeper sleep. The duration of the PWRGD mask is set
to approximately 130 ms by an internal timer. If the voltage
drop is greater than 200 mV during deeper sleep entry or
slow deeper sleep exit, the duration of PWRGD masking is
extended by the internal logic circuit.
Powerup Sequence and Soft−Start
internally. The APD3212/NCP3218/NCP3218G steps
sequentially through each VID code until it reaches the boot
voltage. The powerup sequence, including the soft−start is
illustrated in Figure 20.
The core voltage ramps up linearly to the boot voltage. The
APD3212/NCP3218/NCP3218G regulates at the boot
voltage for approximately 90 ms. After the boot time is over,
CLKEN is asserted low. Before CLKEN is asserted low, the
VID pins are ignored. 9 ms after CLKEN is asserted low,
PWRGD is asserted high.
Current Limit
differential output of a current sense amplifier to a
programmable current limit set point to provide the current
limiting function. The current limit threshold is set by the user
with a resistor connected from the ILIM pin to CSCOMP.
Changing VID On−The−Fly (OTF)
dynamically changing VID code. As a consequence, the
CPU VCC voltage can change without the need to reset the
controller or the CPU. This concept is commonly referred to
as VID OTF transient. A VID OTF can occur with either
light or heavy load conditions. The processor alerts the
controller that a VID change is occurring by changing the
VID inputs in LSB incremental steps from the start code to
the finish code. The change can be either upwards or
downwards steps.
PWRGD
The power−on ramp−up time of the output voltage is set
After EN is asserted high, the soft−start sequence starts.
The
The APD3212/NCP3218/NCP3218G is designed to track
V
CORE
V
BOOT
APD3212/NCP3218/NCP3218G
VCC = 5 V
Figure 20. Powerup Sequence of
EN
APD3212/NCP3218/NCP3218G
t
BOOT
CLKEN
t
CPU_PWRGD
compares
the