NCP3218GMNR2G ON Semiconductor, NCP3218GMNR2G Datasheet - Page 27

• Manufacturer Part Number: NCP3218GMNR2G
• Description: IC CTLR CPU SYNC BUCK 7BIT 48QFN
• Manufacturer: ON Semiconductor
• Series: -r

Specifications of NCP3218GMNR2G

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 3.3 V ~ 22 V
• Number Of Outputs: 1
• Voltage - Output: 0.0125 V ~ 1.5 V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

transient response, the ESR of the bulk capacitor bank (R
should be less than two times the droop resistance, R
C
the VID OTF and/or the deeper sleep exit specifications and
may require less inductance or more phases. In addition, the
switching frequency may have to be increased to maintain
the output ripple.
capacitors (C
change is when the device exits deeper sleep, during which
the V
10 mV. If k = 3.1, solving for the bulk capacitance yields
C
C
+ 21 mF
ESR of 7 mW each yields C
enough to limit the high frequency ringing during a load
change. This is tested using:
Q is limited to the square root of 2 to ensure a critically
damped system.
L
enough to avoid ringing during a load change. If the L
the chosen bulk capacitor bank is too large, the number of
ceramic capacitors may need to be increased to prevent
excessive ringing.
capacitor design can be used if the conditions of
Equations 11, 12, and 13 are satisfied.
Power MOSFETs
power MOSFETs are selected for two high−side switches
and two or three low−side switches per phase. The main
selection parameters for the power MOSFETs are V
Q
gate driver is 5.0 V, logic−level threshold MOSFETs must be
used.
requirement for the low−side (synchronous) MOSFETs. In
X(MIN)
X(MAX)
X
X(MIN)
G
To meet the conditions of these expressions and the
For example, if 30 pieces of 10 mF, 0805−size MLC
Using six 330 mF Panasonic SP capacitors with a typical
Ensure that the ESL of the bulk capacitors (L
For this multimode control technique, an all ceramic
For typical 20 A per phase applications, the N−channel
The maximum output current, I
, C
is about 150 pH for the six SP capacitors, which is low
L
L
where:
CORE
2
1 )
X
X
ISS
v C
v 300 mF
w
v
is greater than C
, C
2
2.1 mW )
22ms
change is 220 mV in 22 ms with a setting error of
Z
RSS
Z
330 nH
3.1
= 300 mF) are used, the fastest VID voltage
, and R
R
2
330 nH
O
1.4375V
220 mV
2
10 mV
27.9 A
(2.1 mW)
(2.1 mW)
DS(ON)
27.9 A
Q
X(MAX)
2
220 mV
X
2
2
490 nH
2
= 1.98 mF and R
. Because the voltage of the
1.4375 V
, the system does not meet
3.1
O
1.4375 V
2 + 2 nH
, determines the R
2.1mW
* 300 mF + 1.0 mF
2
X
−1
= 1.2 mW.
X
) is low
(eq. 13)
O
−300 mF
GS(TH)
DS(ON)
http://onsemi.com
. If the
X
X
of
)
,
27
the APD3212/NCP3218/NCP3218G, currents are balanced
between phases; the current in each low−side MOSFET is
the output current divided by the total number of MOSFETs
(n
expression shows the total power that is dissipated in each
synchronous MOSFET in terms of the ripple current per
phase (I
P
D is the duty cycle and is approximately the output voltage
divided by the input voltage.
I
approximately
allowed power dissipation, the user can calculate the
required R
8−lead SOIC compatible MOSFETs, the junction−to−
ambient (PCB) thermal impedance is 50°C/W. In the worst
case, the PCB temperature is 70°C to 80°C during heavy
load operation of the notebook, and a safe limit for P
about 0.8 W to 1.0 W at 120°C junction temperature.
Therefore, for this example (40 A maximum), the R
MOSFET is less than 8.5 mW for two pieces of low−side
MOSFETs. This R
about 120°C; therefore, the R
less than 6 mW at room temperature, or 8.5 mW at high
temperature.
is the input capacitance and feedback capacitance. The ratio
of the feedback to input must be small (less than 10% is
recommended) to prevent accidentally turning on the
synchronous MOSFETs when the switch node goes high.
two main power dissipation components: conduction losses
and switching losses. Switching loss is related to the time for
the main MOSFET to turn on and off and to the current and
voltage that are being switched. Basing the switching speed
on the rise and fall times of the gate driver impedance and
MOSFET input capacitance, the following expression
provides an approximate value for the switching loss per
main MOSFET:
n
R
C
R
MF
SF
G
ISS
SF
Knowing the maximum output current and the maximum
Another important factor for the synchronous MOSFET
The high−side (main) MOSFET must be able to handle
P
is the inductor peak−to−peak ripple current and is
is the total gate resistance.
). With conduction losses being dominant, the following
+ (1−D)
where:
where:
is the total number of main MOSFETs.
S(MF)
is the input capacitance of the main MOSFET.
R
) and the average total output current (I
+ 2
DS(ON)
f
DS(SF)
I
SW
for the MOSFET. For 8−lead SOIC or
R
n
I
+
SF
O
(1 * D)
V
is also at a junction temperature of
2
DC
) 1
n
L
MF
DS(SF)
12
I
f
O
SW
V
per MOSFET should be
OUT
n
R
n
G
SF
I
R
n
2
MF
n
O
DS(SF)
):
C
(eq. 14)
(eq. 15)
R
ISS
DS(SF)
SF
per
is