PIC10F206-I/OT Microchip Technology, PIC10F206-I/OT Datasheet - Page 15

• Manufacturer Part Number: PIC10F206-I/OT
• Description: MCU 8-Bit PIC10 PIC RISC 768Byte Flash 2.5V/3.3V/5V 6-Pin SOT-23 Bag
• Manufacturer: Microchip Technology

Specifications of PIC10F206-I/OT

• Package: 6SOT-23
• Device Core: PIC
• Family Name: PIC10
• Maximum Speed: 4 MHz
• Ram Size: 24 Byte
• Program Memory Size: 768 Byte
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 3
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 1

3.1
The clock is internally divided by four to generate four
non-overlapping quadrature clocks, namely Q1, Q2,
Q3 and Q4. Internally, the PC is incremented every Q1
and the instruction is fetched from program memory
and latched into the instruction register in Q4. It is
decoded and executed during the following Q1 through
Q4. The clocks and instruction execution flow is shown
in Figure 3-3 and Example 3-1.
FIGURE 3-3:
EXAMPLE 3-1:
© 2007 Microchip Technology Inc.
1. MOVLW 03H
2. MOVWF GPIO
3. CALL
4. BSF
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
Clocking Scheme/Instruction
Cycle
SUB_1
GPIO, BIT1
OSC1
Q1
Q2
Q3
Q4
PC
CLOCK/INSTRUCTION CYCLE
INSTRUCTION PIPELINE FLOW
Q1
Execute INST (PC – 1)
Fetch INST (PC)
Q2
Fetch 1
PC
Q3
Execute 1
Q4
Fetch 2
Q1
Execute INST (PC)
Fetch INST (PC + 1)
Execute 2
PIC10F200/202/204/206
Q2
Fetch 3
PC + 1
3.2
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the PC to change (e.g., GOTO), then two cycles
are required to complete the instruction (Example 3-1).
A fetch cycle begins with the PC incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q3
Execute 3
Q4
Fetch 4
Instruction Flow/Pipelining
Q1
Fetch SUB_1 Execute SUB_1
Execute INST (PC + 1)
Fetch INST (PC + 2)
Q2
Flush
PC + 2
Q3
Q4
DS41239D-page 13
Internal
phase
clock