DS21354LC1+ Maxim Integrated Products, DS21354LC1+ Datasheet - Page 22

• Manufacturer Part Number: DS21354LC1+
• Description: IC TXRX E1 3.3V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21354LC1+

• Function: Single-Chip Transceiver
• Interface: E1, HDLC
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: Remote and AIS Alarm Detector / Generator
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

3.1.4.
Signal Name:
Signal Description:
Signal Type:
This signal is used to asynchronously reset the test access port controller. At power up, JTRST must be
toggled from low to high. This action will set the device into JTAG DEVICE ID mode enabling the test
access port features. This pin has a 10kW pullup resistor. When FMS = 1, this pin is tied low internally.
Tie JTRST low if JTAG is not used and the framer is in DS21354/DS21554 mode (FMS low).
Signal Name:
Signal Description:
Signal Type:
This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various
defined IEEE 1149.1 states. This pin has a 10kW pullup resistor.
Signal Name:
Signal Description:
Signal Type:
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.
Signal Name:
Signal Description:
Signal Type:
Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10kW
pullup resistor.
Signal Name:
Signal Description:
Signal Type:
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin
should be left unconnected.
3.1.5.
Signal Name:
Signal Description:
Signal Type:
A rising edge on this pin causes RSER and RSIG to come out of high-Z state and TSER and TSIG to start
sampling on the next rising edge of RSYSCLK/TSYSCLK beginning an I/O sequence of 8 or 256 bits of
data. This pin has a 10kW pullup resistor.
Signal Name:
Signal Description:
Signal Type:
An output that is set high when the last bit of the 8 or 256 IBO output sequence has occurred on RSER
and RSIG.
JTAG Test Access Port Pins
Interleave Bus Operation Pins
JTRST
IEEE 1149.1 Test Reset
Input
JTMS
IEEE 1149.1 Test Mode Select
Input
JTCLK
IEEE 1149.1 Test Clock Signal
Input
JTDI
IEEE 1149.1 Test Data Input
Input
JTDO
IEEE 1149.1 Test Data Output
Output
CI
Carry In
Input
CO
Carry Out
Output
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