C8051F317-GMR Silicon Laboratories Inc, C8051F317-GMR Datasheet - Page 4

• Manufacturer Part Number: C8051F317-GMR
• Description: MCU 8-Bit C8051F31x 8051 CISC 16KB Flash 3.3V 24-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F317-GMR

• Package: 24QFN EP
• Device Core: 8051
• Family Name: C8051F31x
• Maximum Speed: 25 MHz
• Ram Size: 1.25 KB
• Program Memory Size: 16 KB
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 21
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 17-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4

C8051F310/1/2/3/4/5/6/7
9. Reset Sources....................................................................................................... 105
10. Flash Memory ..................................................................................................... 111
11. External RAM ........................................................................................................ 119
12. Oscillators ............................................................................................................. 121
13. Port Input/Output ................................................................................................ 129
14. SMBus ................................................................................................................... 145
4
8.4. Power Management Modes ............................................................................ 102
9.1. Power-On Reset ............................................................................................. 106
9.2. Power-Fail Reset / V
9.3. External Reset ................................................................................................ 107
9.4. Missing Clock Detector Reset......................................................................... 108
9.5. Comparator0 Reset......................................................................................... 108
9.6. PCA Watchdog Timer Reset........................................................................... 108
9.7. Flash Error Reset............................................................................................ 108
9.8. Software Reset ............................................................................................... 108
10.1.Programming The Flash Memory ................................................................... 111
10.2.Non-volatile Data Storage .............................................................................. 112
10.3.Security Options ............................................................................................. 113
10.4.Flash Write and Erase Guidelines .................................................................. 115
12.1.Programmable Internal Oscillator ................................................................... 121
12.2.External Oscillator Drive Circuit...................................................................... 124
12.3.System Clock Selection.................................................................................. 124
12.4.External Crystal Example ............................................................................... 126
12.5.External RC Example ..................................................................................... 127
12.6.External Capacitor Example ........................................................................... 127
13.1.Priority Crossbar Decoder .............................................................................. 131
13.2.Port I/O Initialization ....................................................................................... 133
13.3.General Purpose Port I/O ............................................................................... 135
14.1.Supporting Documents ................................................................................... 146
14.2.SMBus Configuration...................................................................................... 146
14.3.SMBus Operation ........................................................................................... 146
8.3.4. Interrupt Latency ...................................................................................... 95
8.3.5. Interrupt Register Descriptions................................................................. 97
8.4.1. Idle Mode................................................................................................ 102
8.4.2. Stop Mode .............................................................................................. 103
10.1.1.Flash Lock and Key Functions ............................................................... 111
10.1.2.Flash Erase Procedure .......................................................................... 111
10.1.3.Flash Write Procedure ........................................................................... 112
10.4.1.V
10.4.2.PSWE Maintenance ............................................................................... 115
10.4.3.System Clock ......................................................................................... 116
14.3.1.Arbitration............................................................................................... 147
14.3.2.Clock Low Extension.............................................................................. 148
14.3.3.SCL Low Timeout................................................................................... 148
14.3.4.SCL High (SMBus Free) Timeout .......................................................... 148
DD
Maintenance and the V
DD
Monitor...................................................................... 106
Rev. 1.7
DD
Monitor ................................................. 115