DS2172TN+ Maxim Integrated Products, DS2172TN+ Datasheet
DS2172TN+
Specifications of DS2172TN+
Related parts for DS2172TN+
DS2172TN+ Summary of contents
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FEATURES Generates/Detects digital bit patterns for analyzing, evaluating and troubleshooting digital communications systems Operates at speeds from MHz Programmable polynomial feedback taps for generation of any other pseudorandom pattern bits in length 6 ...
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GENERAL OPERATION 1.1 PATTERN GENERATION The DS2172 is programmed to generate a particular test pattern by programming the following registers: - Pattern Set Registers (PSR) - Pattern Length Register (PLR) - Polynomial Tap Register (PTR) - Pattern Control Register ...
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DS2172 FUNCTIONAL BLOCK DIAGRAM Figure 1 DS2172 PATTERN GENERATION BLOCK DIAGRAM Figure 2 NOTES: 1. Tap A always equals length (N-1) of pseudorandom or repetitive pattern. 2. Tab B can be programmed to any feedback tap for pseudorandom pattern generation. ...
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DETAILED PIN DESCRIPTION Table 1 PIN SYMBOL TYPE DESCRIPTION AD0 I/O 3 AD1 I/O 4 TEST AD2 I/O 7 AD3 I/O 8 AD4 I/O 9 AD5 I/O 10 AD6 I/O ...
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PIN SYMBOL TYPE DESCRIPTION RDATA I 26 RDIS I 27 RCLK TCLK I 31 TDIS I 32 TDATA O DS2172 REGISTER MAP Table 2 ADDRESS R/W ...
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PARALLEL CONTROL INTERFACE The DS2172 is controlled via a multiplexed bi-directional address/data bus by an external microcontroller or microprocessor. The DS2172 can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel ...
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SYMBOL POSITION - PLR1.7 - PLR1.6 - PLR1.5 LB4 PLR1.4 LB3 PLR1.3 LB2 PLR1.2 LB1 PLR1.1 LB0 PLR1.0 5.0 POLYNOMIAL TAP REGISTER Polynomial Tap Bits PT4 - PT0 determine the feedback position of Tap B connected to the XOR input ...
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PATTERN CONTROL REGISTER The Pattern Control Register (PCR) is used to configure the operating parameters of the DS2172 and to control the patterns being generated and received. Also the PCR is used to control the pattern synchronizer and the ...
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ERROR INSERT REGISTER The Error Insertion Register (EIR) controls circuitry within the DS2172 that allows the generated pattern to be intentionally corrupted. Bit errors can be inserted automatically at regular intervals by properly programming the EIR0 to EIR2 bits ...
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PSEUDORANDOM PATTERN GENERATION (PCR.5=1) Table 4 PATTERN TYPE Fractional T1 LB Activate ...
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NOTES FOR TABLES 4 AND 5: 1. PTR = Polynomial Tap Register (address = 05) 2. PLR = Pattern Length Register (address = 04) 3. PSR3 = Pattern Set Register 3 (address = 00) 4. PSR2 = Pattern Set Register ...
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PATTERN RECEIVE REGISTERS The Pattern Receive Register (PRR) provides access to the data patterns received at RDATA. The operation of these registers depends on the synchronization status of the DS2172. Asserting the RL bit (PCR.3) or pin during an ...
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SR: STATUS REGISTER (Address=14 Hex) (MSB) - RA1 SYMBOL POSITION NAME AND DESCRIPTION - SR.7 Not Assigned. Could be any value when read. RA1 SR.6 Receive All Ones. Set when 32 consecutive 1s are received; allowed to be cleared when ...
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IMR: INTERRUPT MASK REGISTER (Address=15 Hex) (MSB) - RA1 SYMBOL POSITION NAME AND DESCRIPTION - IMR.7 Not Assigned. Should be set to 0 when written to. RA1 IMR.6 Receive All 1s interrupt masked 1 = interrupt enabled RA0 ...
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AC TIMING AND DC OPERATING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature for DS2172TN Storage Temperature Soldering Temperature * This is a stress rating only and functional operation of the device at these ...
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AC CHARACTERISTICS - PARALLEL PORT PARAMETER Cycle Time Pulse Width, DS Low or RD Pulse Width, DS High or RD Input Rise/Fall Times R/ Hold Times W R/ Setup Time Before DS High W Setup Time Before DS ...
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INTEL BUS READ AC TIMING (BTS=0) Figure 3 ALE PW t ASD WR t ASD AD0-AD7 t CYC ASH t ASED ASL DDR t AHL ...
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INTEL BUS WRITE AC TIMING (BTS=0) Figure 4 ALE PW t ASD RD t ASD AD0-AD7 t CYC ASH t ASED ASL t DSW t AHL ...
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MOTOROLA BUS AC TIMING (BTS=1) Figure ASD DS PW R/W AD0-AD7 (READ) CS AD0-AD7 (WRITE) ASH ASED EL t CYC t RWS t ASL t DDR t AHL ASL t ...
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AC CHARACTERISTICS - RECEIVE SIDE PARAMETER RCLK Period RCLK Pulse Width RDATA Set Up to RCLK Rising RDATA Hold from RCLK Rising RDIS Set Up to RCLK Rising RDIS Hold from RCLK Rising RL and LC Pulse Width RCLK Rise ...
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RECEIVE AC TIMING Figure 6 TRANSMIT AC TIMING Figure 7 NOTE: When TDIS is high about the rising edge of TCLK, TDATA will not be updated and will be held with the previous valve until TDIS is low about the ...
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DS2172 32-PIN TQFP DIM MIN MAX A - 1.20 A1 0.05 0.15 A2 0.95 1.05 D 8.80 9.20 D1 7.00 BSC E 8.80 9.20 E1 7.00 BSC L 0.45 0.75 e 0.80 BSC B 0.30 0.45 C 0.09 0.20 22 ...