DS21554L Maxim Integrated Products, DS21554L Datasheet - Page 70

• Manufacturer Part Number: DS21554L
• Description: IC TXRX E1 1-CHIP 5V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21554L

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: Remote and AIS Alarm Detector / Generator
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

14.
The DS21354/DS21554 can extract/insert data from/into the Sa bit positions (Sa4 to Sa8) or from/to any
multiple of DS0 or sub-DS0 channels. The SCT contains a complete HDLC controller (see Section 14).
14.1.
The DS21354/DS21554 contain a complete HDLC controller with 64-byte buffers in both the transmit
and receive directions The HDLC controller performs all the necessary overhead for generating and
receiving an HDLC formatted message.
The HDLC controller automatically generates and detects flags, generates and checks the CRC check
sum, generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns
to the HDLC data stream.
There are 11 registers that the host uses to operate and control the operation of the HDLC controller. A
brief description of the registers is shown in
Table 14-1. HDLC Controller Register List
HDLC Control Register (HCR)
HDLC Status Register (HSR)
HIMR Interrupt Mask Register (HIMR)
Receive HDLC Information register (RHIR)
Receive HDLC FIFO Register (RHFR)
Receive HDLC DS0 Control Register 1 (RDC1)
Receive HDLC DS0 Control Register 2 (RDC2)
Transmit HDLC Information register (THIR)
Transmit HDLC FIFO Register (THFR)
Transmit HDLC DS0 Control Register 1 (TDC1)
Transmit HDLC DS0 Control Register 2 (TDC2)
HDLC CONTROLLER FOR THE Sa BITS OR DS0
General Overview
NAME
Table
70 of 124
14-1.
general control over the HDLC controller
key status information for both transmit and receive
directions allows/stops status bits to/from causing an
interrupt
status information on receive HDLC controller
access to 64–byte HDLC FIFO in receive direction
controls the HDLC function when used on DS0
channels
controls the HDLC function when used on DS0
channels
status information on transmit HDLC controller
access to 64–byte HDLC FIFO in transmit direction
controls the HDLC function when used on DS0
channels
controls the HDLC function when used on DS0
channels
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
FUNCTION