SI3200-FS Silicon Laboratories Inc, SI3200-FS Datasheet
SI3200-FS
Specifications of SI3200-FS
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SI3200-FS Summary of contents
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... IC performs all high-voltage functions and operates from a 3 supply as well as single or dual battery supplies up to 100 V. The Si3220 and Si3225 are available in a 64-pin thin quad flat package (TQFP), and the Si3200 is available in a thermally-enhanced 16-pin small outline (SOIC) package. ...
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... Si3220/Si3225 ® Dual ProSLIC Selection Guide Part Description Number Si3200-KS Linefeed interface Si3200-BS Linefeed interface Si3200-FS Linefeed interface Si3200-GS Linefeed interface Si3220-FQ Dual ProSLIC Si3220-GQ Dual ProSLIC Si3225-FQ Dual ProSLIC Si3225-GQ Dual ProSLIC 2 On-Chip External Pulse Ringing Ringing Metering Support Rev. 1.0 ...
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... SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 PCM Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 General Circuit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 System Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Pin Descriptions: Si3220/ Pin Descriptions: Si3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Package Outline: 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Package Outline: 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Silicon Labs Si3220/25 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Related Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Contact Information ...
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... Si3220/Si3225 Electrical Specifications Table 1. Absolute Maximum Ratings and Thermal Information Parameter Supply Voltage, Si3200 and Si3220/Si3225 High Battery Supply Voltage, Si3200 Low Battery Supply Voltage, Si3200 TIP or RING Voltage, Si3205 TIP, RING Current, Si3200 STIPAC, STIPDC, SRINGAC, SRINGDC Current, Si3220/Si3225 Input Current, Digital Input Pins ...
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... Supply Voltage, Si3220/Si3225 Supply Voltage, Si3200 High Battery Supply Voltage, Si3200 Low Battery Supply Voltage, Si3200 *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 Table 3 ...
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... Supply Cur- I BAT VBAT rent (Si3200) Notes: 1. All specifications are for a single channel based on measurements with both channels in the same operating state. 2. See "Ringing Power Considerations" on page 50 for current and power consumption under other operating conditions. 3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must ...
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Table 3. 3.3 V Power Supply Characteristics = = ( –V 3 °C for K/F-Grade, – °C for B/G-Grade) DD DD1 DD4 A Parameter Symbol Chipset Power P SLEEP Consumption P ...
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... Supply Current I DD VDD (Si3200) Notes: 1. All specifications are for a single channel based on measurements with both channels in the same operating state. 2. See "Ringing Power Considerations" on page 50 for current and power consumption under other operating conditions. 3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must ...
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... Table Power Supply Characteristics = = ( – °C for K/F-Grade, – °C for B/G-Grade) DD DD1 DD4 A Parameter Symbol V Supply Current I BAT VBAT (Si3200) Chipset Power P SLEEP Consumption P OPEN P STBY P STBY P ACTIVE P ACTIVE P OHT P OHT P RING Notes: 1. All specifications are for a single channel based on measurements with both channels in the same operating state. ...
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Si3220/Si3225 Table 5. AC Characteristics = ( –V 3. °C for K/F-Grade, – °C for B/G-Grade) DD DD1 DD4 A Parameter Overload Level Overload Compression 1 Single Frequency ...
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Table 5. AC Characteristics (Continued –V 3. °C for K/F-Grade, – °C for B/G-Grade) DD DD1 DD4 A Parameter 5 Transhybrid Balance 6 Idle Channel Noise ...
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Si3220/Si3225 Table 6. Linefeed Characteristics = ( –V 3. DD1 DD4 A Parameter Maximum Loop Resistance (adaptive 1 linefeed disabled ) Maximum Loop Resistance (adaptive 1 linefeed enabled ) DC Loop Current Accuracy ...
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... DD1 DD4 A Parameter Symbol Resolution Differential Nonlinearity DNL Integral Nonlinearity INL Gain Error Table 8. Si3200 Characteristics = = (V 3. °C for K/F-Grade, – °C for B/G-Grade Parameter TIP/RING Pulldown Transistor Satura- tion Voltage TIP/RING Pullup Transistor Saturation Voltage Battery Switch Saturation ...
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... Si3220/Si3225 Table 8. Si3200 Characteristics (Continued 3. °C for K/F-Grade, – °C for B/G-Grade Parameter OPEN State TIP/RING Leakage Current Internal Blocking Diode Forward Voltage Notes 600 Ω 2 LOAD OUT Table 9. DC Characteristics ( – DD1 DD4 Parameter Symbol High Level Input ...
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Table 10. DC Characteristics ( – DD1 DD4 Parameter Symbol High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage SDITHRU internal pullup ...
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Si3220/Si3225 Table 12. Switching Characteristics—SPI 3. °C for K/F-Grade, – °C for B/G-Grade, C DDA DDA A Parameter Cycle Time SCLK Rise Time, SCLK Fall Time, ...
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Table 13. Switching Characteristics—PCM Highway Interface = = ( –V 3. DD1 DD4 A Parameter PCLK Period Valid PCLK Inputs 2 FSYNC Period PCLK Duty Cycle Tolerance PCLK Period Jitter Tolerance Rise Time, ...
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Si3220/Si3225 PCLK FSYNC DRX DTX Figure 2. PCM Highway Interface Timing Diagram Rev. ...
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Table 14. Switching Characteristics—GCI Highway Serial Interface = = ( –V 3. DD1 DD4 A 1 Parameter PCLK Period (2.048 MHz PCLK Mode) PCLK Period (4.096 MHz PCLK Mode) 2 FSYNC Period PCLK ...
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Si3220/Si3225 PCLK t su1 FSYNC Frame 0, DRX Bit 0 DTX Figure 4. GCI Highway Interface Timing Diagram (4.096 MHz PCLK Mode) Acceptable Region Figure 5. Transmit and Receive Path SNDR ...
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Fundamental 5 Output Power (dBm0 2 Figure 6. Overload Compression Performance 5 0 −5 −10 −15 −20 −25 −30 −35 −40 −45 0 250 500 750 1000 1250 1500 1750 2000 ...
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Si3220/Si3225 5 0 −5 −10 −15 −20 −25 −30 −35 −40 −45 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 ...
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TX Group Delay Distortion 1100 1000 900 800 700 600 500 400 300 200 100 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 Frequency (Hz) Figure 9. Transmit Group Delay ...
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Si3220/Si3225 24 Rev. 1.0 ...
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BATSELa 49 TRD2a 50 TRD1a THERMa 54 IRINGPa 55 GND1 56 VDD1 57 ITIPPa 58 IRINGNa 59 ITIPNa 60 SRINGDCa 61 SRINGACa 62 STIPACa 63 STIPDCa Si3220/Si3225 BATSELb ...
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Si3220/Si3225 BATSELa 49 TRD2a 50 TRD1a 51 RTRPa 52 BLKRNG 53 THERMa 54 IRINGPa 55 GND1 56 VDD1 57 ITIPPa 58 IRINGNa 59 ITIPNa 60 SRINGDCa 61 SRINGACa 62 STIPACa 63 STIPDCa BATSELb 32 RRDb 31 ...
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... R20, R22 15 Ω , 1/8 W, ±5% R21, R23 39 k Ω , 1/10 W, ±5% R24, R25 Table 16. Si3225 + Si3200 External Component Values Component C1, C2, C11, C12 100 nF, 100 V, X7R, ±20% Filter capacitors for TIP, RING ac sensing inputs. C3, C4, C13, C14 10 nF, 100 V, X7R, ±20% 1 µ ...
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... The Si3220 and Si3225 are available in a 64-lead TQFP, and the Si3200 is available in a thermally-enhanced 16-lead SOIC. Dual ProSLIC Architecture The Dual ProSLIC chipset is comprised of a low-voltage CMOS device that uses a low-cost integrated linefeed ...
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... R DC RING; Capacitor C the TIP and RING leads to be measured. The Si3220 and Si3225 both use the Si3200 to drive TIP and RING and isolate the high-voltage line from the low-voltage CMOS devices. The Si3220 and Si3225 measure voltage at various nodes to monitor the linefeed current. R provide these measuring points ...
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... Figure 15. Simplified Dual ProSLIC Linefeed Architecture for TIP and RING Leads (Diagram Illustrates either TIP or RING Lead of a Single Channel) 30 Low Frequency Diagnostic Filters Monitor A/D A/D DSP D/A SLIC DAC Σ SLIC Control SLIC Control Loop Si3200 Battery Current Select Mirror Control Rev. 1.0 Si3220/ Si3225 V Sense BAT R BAT ...
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... Monitoring and Power Fault Detection" on page 35 for Open (LF[2:0] = 000). The Si3200 output is high-impedance. This mode can be used in the presence of line fault conditions and to generate open-switch intervals (OSIs). The device can also automatically enter the Open state if excess power consumption is detected in the Si3200 or in the discrete bipolar transistors. ...
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Si3220/Si3225 Table 18. Register and RAM Locations for Linefeed Control Parameter Mnemonic Linefeed LINEFEED Linefeed Shadow LINEFEED Battery Feed Control Loop Current Limit On-Hook Line Voltage Common Mode Voltage V Delta for Off-Hook VOCDELTA OC V Delta Threshold, Low OC ...
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... Figure 16. Adaptive Linefeed V/I Behavior When the Si3220/Si3225 is used with the Si3200 linefeed device, the source impedance of the dc feed is 640 Ω before the adaptive linefeed transition and 320 Ω after the adaptive linefeed transition, as shown in Figure 16. On the other hand, when the Si3220/Si3225 is used with a discrete bipolar transistor linefeed the source impedance of the dc feed is 320 Ω ...
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... Si3220/Si3225 VOC voltage boost associated with a non-zero VOCDELTA value. With VOCDELTA = 0 in the case of the Si3200, the adaptive linefeed transition still changes the source impedance from 640 Ω to 320 Ω , and there is a corresponding discontinuity at the transition point. In the case of the discrete bipolar linefeed, since the source impedance is 320 Ω ...
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... The Dual ProSLIC devices can prevent thermal overloads by regulating the total power inside the Si3200 or in each of the external bipolar transistors (if using a discrete linefeed circuit). The DSP engine performs all power calculations and provides the ability ...
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Si3220/Si3225 Table 20. Register and RAM Locations Used for Loop Monitoring Parameter Register/RAM Mnemonic Loop Voltage Sense VLOOP (V – TIP RING TIP Voltage Sense VTIP RING Voltage Sense VRING Loop Current Sense ILOOP Battery Voltage Sense VBAT ...
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... PQ1E–PQ6E bits in the IRQEN3 register. Si3200 Power Calculation When using the Si3200 also possible to detect the thermal conditions of the linefeed circuit by calculating the total power dissipated within the Si3200. This case is similar to the transistor power equations case, with ...
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... PQ1S to PQ6S bits of the IRQVEC3 register are set when a power alarm is triggered in the respective transistor. When using the Si3200, the PQ1E bit enables the power alarm interrupt, and the PQ1S bit is set when a Si3200 power alarm is triggered. 38 THERMAL ...
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... Q1–Q6 Power Alarm Interrupt Pending Q1–Q6 Power Alarm Interrupt Enable Power Dissipation Considerations The Dual ProSLIC devices rely on the Si3200 to power the line from the battery supply. The PCB layout and enclosure conditions should be designed to allow sufficient thermal dissipation out of the Si3200, and a programmable power alarm threshold ensures product safety under all operating conditions. See " ...
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Si3220/Si3225 Automatic Dual Battery Switching The Dual ProSLIC chipsets provide the ability to switch between several user-provided battery supplies to aid thermal management. Two specific scenarios where this method may be required follow: Ringing to off-hook state transition (Si3220): During ...
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... BRING 0.1 µF V BLO V BHI Figure 20. 3-Battery Switching with Si3220/Si3200 –24 V) rails using the switch internal to the Si3200. The Si3220’s GPO pin is used along with the external transistor circuit to switch the V voltage battery rail) onto the Si3200’s V the ability to ringing is enabled ...
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... Q2, Q5 and Q6 – note that the Si3200 has corresponding MOS transistors). The same I equation applies to the discrete bipolar linefeed LOOP as well as the Si3200 linefeed device. The following equation is conditioned by the CMH status bit in register LCRRTP and by the linefeed state as indicated by the LFS field in the LINEFEED register. I ...
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... LONG in the following equation. Refer to Figure 18 on page 36 for the transistor references used in the equation (Q1, Q2, Q5 and Q6 – note that the Si3200 has corresponding MOS transistors). The same I equation applies to the discrete bipolar linefeed as well as the Si3200 linefeed device. ...
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Si3220/Si3225 The output of the low-pass filter is compared to the programmable threshold, LONGHITH. Hysteresis is enabled by programming a LONGLOTH, to detect when the ground key is released. The threshold comparator output feeds a programmable debounce filter. The output ...
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I Q1 Input LONG Signal I Processor LFS Figure 22. Ground Key Detection Circuitry Table 27. Register and RAM Locations Used for Ground Key Detection Register/ Parameter RAM Mnemonics Ground Key Interrupt IRQVEC2 Pending ...
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... Adding dc offset to the ringing signal decreases the maximum possible ringing amplitude. Adding significant dc offset also increases the power dissipation in the Si3200 and may require additional airflow or modified PCB layout to maintain acceptable operating temperatures in the line feed circuitry. The Dual ProSLIC chipset automatically ...
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Table 28. Register and RAM Locations Used for Ringing Generation Parameter Register/RAM Mnemonic Ringing Waveform RINGCON Ringing Active Timer Enable RINGCON Ringing Inactive Timer RINGCON Enable Ringing Oscillator Enable RINGCON Monitor Ringing Oscillator Active RINGTALO/ Timer RINGTAHI Ringing Oscillator Inactive ...
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Si3220/Si3225 Internal Sinusoidal Ringing A sinusoidal ringing waveform is generated by the on- chip digital tone generator. The tone generator used to generate ringing tones is a two-pole resonator with a programmable frequency and amplitude. Since ringing frequencies are low ...
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V RING Si3220 DC Offset GND V TIP DC Offset V OFF -80V V RING V BATR Figure 25. Internal Unbalanced Ringing To enable unbalanced ringing, set the RINGUNB bit of the RINGCON register. As with internal balanced ringing, the ...
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... If an offset of the ringing signal from the ring lead is desired, VOVR can be used for this purpose. Ringing Power Considerations The total power consumption of the Si3220/Si3200 chipset using internal ringing generation is dependent on the VDD supply voltage, the desired ringing amplitude, the total loop impedance, and the ac load impedance (number of REN) ...
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Ringtrip Timeout Counter The Dual ProSLIC incorporates a ringtrip timeout counter, RTCOUNT, that will monitor the status of the ringing control. When exiting ringing, the Dual ProSLIC will allow the ringtrip timeout counter a sufficient amount of time (RTCOUNT x ...
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Si3220/Si3225 Table 29. Recommended Values for Ring Trip Registers and RAM Addresses Ringing Ringing DC Method Frequency Offset Added? Yes 16– Internal Yes (Si3220) 33– External 16–32 Hz Yes (Si3225) 33–60 Hz Yes Notes: 1. All ...
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The Si3220 also can add a dc offset component to the ringing signal and detect a ring trip event by monitoring the dc loop current flowing once the terminal equipment transitions to the off-hook state. Although adding dc offset reduces ...
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Si3220/Si3225 Si3220/ Si3225 Figure 29. Driving Relays with V The maximum allowable R MaxR DRV Table 31. Recommended R ProSLIC V Relay V DD 3.3 V ±5% 3.3 V ± ± ±5% 3.3 V ±5% 5 ...
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Si3220/Si3225 Rev. 1.0 55 ...
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... Figure 30 illustrates the 56 RING Protection Si3200 TIP timing sequence for a typical ringing relay control application. During a typical ringing sequence, the Si3225 monitors both the ringing relay current (IRNGNG) and the RINGEN bit of the RINGCON register ...
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Setting the linefeed register to the opposite polarity immediately reverses (hard reversal) the line polarity. For example, to transition from Forward Active mode to Reverse Active mode changes LF[2:0] from 001 to 101. Polarity reversal is accommodated in the OHT ...
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Si3220/Si3225 Two-Wire Impedance Synthesis Two-wire impedance synthesis is performed on-chip to optimally match the output impedance of the Dual ProSLIC to the impedance of the subscriber loop to minimize the receive path signal reflected back onto the transmit path. The ...
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FIR and IIR filter blocks. The transhybrid balance filters can be disabled to implement loopback diagnostic modes. To disable the transhybrid balance filter (zero cancellation), set the HYBDIS bit in the DIGCON register to 1. ...
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Si3220/Si3225 2 π 852 ---------------- - coeff = cos = 1 8000 OSC1FREQ = 0.78434 0.21556 15 × ( OSC1AMP = -------------------- - 2 – 1.78434 ...
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Table 34. Register and RAM Locations Used for Tone Generation Parameter Oscillator 1 Frequency Coefficient Oscillator 1 Amplitude Coefficient Oscillator 1 Initial Phase Coefficient Oscillator 1 Active Timer Oscillator 1 Inactive Timer Oscillator 1 Control IRQVEC1, IRQEN1 Oscillator 1 Interrupts ...
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Si3220/Si3225 OSC1EN ... ... 0,1 , OSC1TA ENSYNC1 Tone Gen. 1 Signal Output Figure 36. Tone Generator Timing Diagram First Ring Burst Message Message Parameter 1 Type Length Message Header Parameter Type Figure 37. On-Hook Caller ID Transmission Sequence 62 ...
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Tone Generator Interrupts Both the active and inactive timers can generate an interrupt to signal “on/off” transitions to the software. The timer interrupts for tone generator 1 can be individually enabled by setting the OS1TAE and OS1TIE bits. Timer interrupts ...
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Si3220/Si3225 Pulse Metering Generation The Si3220 offers an additional tone generator to generate tones above the audio frequency band. This oscillator generates billing tones that are typically 12 kHz or 16 kHz. The generator follows the same algorithm as described ...
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BUF A Figure 38. Pulse Metering Generation Block Diagram DTMF Detection On-chip DTMF detection, also known as touch tone, is available in the Si3220 and Si3225 in-band signaling system that replaces the pulse- ...
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Si3220/Si3225 Table 39 outlines the hex codes corresponding to the detected DTMF digits. Table 39. DTMF Hex Codes Digit Hex code 0x1 1 0x2 2 0x3 3 0x4 4 0x5 5 0x6 6 0x7 7 0x8 8 0x9 9 0xA ...
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TXGAIN or RXGAIN settings. TXEQ/RXEQ Equalizer Blocks The TXEQ and RXEQ blocks (see Figure 11 on page 24) represent 4-tap filters that can ...
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Si3220/Si3225 64 -------------- - T = settle f PCLK PCLK PFD RESET Figure 40. PLL Frequency Synthesizer Interrupt Logic The Dual ProSLIC devices are capable of generating interrupts for the following events: Loop current/ring ground detected Ring trip detected Ground ...
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CS pin. CS must be asserted before the falling edge of SCLK on which the first bit of data is expected during a read cycle and must remain low for the duration of the 8-bit transfer (command/ address or ...
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Si3220/Si3225 SDO CS CPU SDI SPI Clock 70 Channel 0 CS SDO Channel 1 SCLK Channel 2 CS SDO Channel 3 SCLK Channel 14 CS SDO Channel 15 SCLK Figure 41. SPI Daisy-Chain Mode Rev. 1.0 SDI0 SDI SDI1 Dual ...
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In Figure 42, the CID field is zero. As this field is decremented (in LSB to MSB order), the value decrements for each SDI down the line. The BRDCST, R/W, and REG/RAM bits remain unchanged as the control word passes ...
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Si3220/Si3225 CS SCLK SDI CONTROL SDO Figure 44. Register Read Operation via an 8-Bit SPI Port Figures 45 and 46 illustrate WRITE and READ operations to register addresses via a 16-bit SPI controller. These operations require a 4-byte transfer arranged ...
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A RAM access interrupt in each channel indicates that the pending RAM access request is serviced. For a RAM access, the ADDRESS and DATA is transferred from the SPI registers to the address and data buffers in the appropriate channel. ...
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Si3220/Si3225 CS SCLK SDI CONTROL SDO Figure 50. RAM Read Operation via a 16-Bit SPI Port PCM Interface The Dual ProSLIC devices programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled by the ...
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PCLK FSYNC PCLK_CNT 0 1 DRX MSB DTX HI-Z MSB Figure 52. Example, Timeslot 1, Long FSYNC (TXS/RXS PCM Companding The Dual ProSLIC devices support both µ-255 Law (µ- Law) and A-Law companding formats in addition to Linear Data mode. ...
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Si3220/Si3225 PCLK FSYNC PCLK_CNT 0 1 DRX MSB DTX HI-Z MSB Figure 54. 16-Bit Linear Mode Example, Timeslots 1 and 2, Long FSYNC Rev. 1 ...
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Table 41. µ-Law Encode-Decode Characteristics Segment #Intervals X Interval Size Number 256 128 ...
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Si3220/Si3225 Table 42. A-Law Encode-Decode Characteristics Segment #intervals X interval size Number 128 ...
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General Circuit Interface The Dual ProSLIC devices also contain an alternate communication interface to the SPI and PCM control and data interface. The general circuit interface (GCI) is used for the transmission and reception of both control and data information ...
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Si3220/Si3225 handshaking bits, MR and MX. The C/I bits indicate status and command communication handshaking bits Monitor Receive, MR, and Monitor Transmit, MX, exchange data in the Monitor channel. Figure 55 illustrates the contents of a GCI highway frame. 16-Bit ...
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Monitor Channel The Monitor channel is used for initialization and setup of the Dual ProSLIC devices also used for general communication with the Dual ProSLIC by allowing read and write access to the Dual ProSLIC devices registers. Use ...
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Si3220/Si3225 The Idle state is achieved by the MX and MR bits being held inactive for two or more frames. When a transmission is initiated by a host device, an active state is seen on the downstream MX bit. This ...
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Idle Rec eiv alid New ...
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Si3220/Si3225 Idle RQT RQT RQT nth ...
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Figures 60 and 61 are example timing diagrams of a register read and a register write to the Dual ProSLIC using the GCI. As noted in Figure 59, the transmitter should always anticipate the acknowledgement of the receiver for correct ...
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Si3220/Si3225 Monitor Data Downstream $01 $FF $FF $91 $91 125 µs 1 Frame MX Downstream Bit MR Downstream Bit Monitor Data Upstream $FF $FF $FF $FF $FF MX Upstream Bit MR Upstream Bit = Acknowledgement of data reception Figure 61. ...
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Programming the Dual ProSLIC Using the Monitor Channel The Dual ProSLIC devices use the monitor channel to Transfer status or operating mode information to and from the host processor. Communication with the Dual ProSLIC should be in the following format: ...
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Si3220/Si3225 monitor channel section. This section defines the functionality of the six C/I bits whether they are being transmitted to the GCI bus via the DTX pin (upstream) or received from the GCI bus via the DRX pin (downstream). The ...
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... The transition to the OPEN state stemming from power alarm detection is intended to protect the Dual ProSLIC circuit in the event that too much power is dissipated in the Si3200 LFIC. This alarm is typically due to a fault in the application circuit or on the subscriber loop but can be caused by intermittent power spikes depending on the threshold to which the alarm is set ...
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Si3220/Si3225 cycles. If the Dual ProSLIC continues to automatically transition to the OPEN state, the power alarm threshold might be set incorrectly. If this problem persists after the power alarm settings are verified, a system fault is probable, and the ...
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The interrupt information for channels A and single bit that indicates that one or more interrupts might exist on the respective channel. Each of the individual interrupt flags (see registers 18–20) can be individually masked by writing ...
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Si3220/Si3225 Table 50. Summary of Signal Generation and Measurement Tools Function DC Current Generation DC Voltage Generation Audio Tone Generation Ringing Signal Generation 8-Bit dc/Low-Frequency Monitor A/D Converter Programmable Timer AC Low-Pass Filter 16-Bit Audio A/D Converter Transmit Path Notch ...
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VTIP VRING VLOOP VLONG ILOOP ILONG VRING,EXT IRING,EXT Figure 64. SLIC Diagnostic Filter Structure Measurement Tools 8-Bit monitor A/D converter. This 8-bit A/D converter monitors all dc and low-frequency voltage and current data from TIP to ground and RING to ...
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Si3220/Si3225 Programmable timer. The Dual ProSLIC devices incorporate several digital oscillator circuits to program the on and off times of the ringing and pulse-metering signals. The tone generation oscillator can be used to program a time period for averaging specific ...
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Line capacitance measurement. Implemented like the ac line impedance measurement test above, but the frequency band of interest is between 1 kHz and 3.4 kHz. Knowing the synthesized 2-wire impedance of the Dual ProSLIC, the roll-off effect can be used ...
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Si3220/Si3225 Pin Descriptions: Si3220/ SVBATa 1 RPOa 2 RPIa 3 RNIa 4 RNOa 5 CAPPa 6 Si3220 CAPMa 7 QGND 8 64-Lead TQFP IREF 9 (epad) CAPMb 10 ...
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... Positive RING Current Control. Analog current output drives dc current onto RING side of sub- scriber loop in reverse polarity. Also modulates ac current onto RING side of loop. I Temperature Sensor. Senses Internal temperature of Si3200. Connect to THERM pin of Si3200 when using discrete linefeed circuit Test Relay Driver Output. ...
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Si3220/Si3225 Symbol Pin Number(s) Si3220 Si3225 28, 52 28, 52 RTRPb, RTRPa 30, 50 30, 50 TRD2b, TRD2a 31, 48 RRDb, RRDa 31, 48 GPOb, GPOa 32, 49 32, 49 BATSELb, BATSELa 35 35 DRX 36 36 DTX ...
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Symbol Pin Number(s) Si3220 Si3225 46 46 SDITHRU BLKRNG epad epad GND Input/ Description Output O Serial Data Daisy Chain. Enables multiple devices to use a single CS for serial port con- trol. Connect SDITHRU pin ...
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... RING Output. Connect to the RING lead of the subscriber loop. Operating Battery Voltage. Si3200 internal system battery supply. Connect SVBATa/b pin from Si3220/ 25 and decouple with a 0.1 µF/100 V filter capacitor. High Battery Voltage. Connect to the system ringing battery supply. Decouple with a 0.1 µF/100 V filter capacitor ...
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Pin #(s) Symbol Input/ Description Output 12 IRINGN I Negative RING Current Control. Connect to the IRINGN lead of the Si3220 or Si3225. 13 IRINGP I Positive RING Current Drive. Connect to the IRINGP lead of the Si3220 or Si3225. ...
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Si3220/Si3225 Package Outline: 64-Pin TQFP Figure 65 illustrates the package details for the Dual ProSLIC. Table 51 lists the values for the dimensions shown in the illustration See ...
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... Package Outline: 16-Pin ESOIC Figure 66 illustrates the package details for the Si3200. Table 52 lists the values for the dimensions shown in the illustration Seating Plane Figure 66. 16-Pin Thermal Enhanced Small Outline Integrated Circuit (ESOIC) Package Table 52. Package Diagram Dimensions E H θ L Bottom Side Exposed Pad 2 ...
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... Dual ProSLIC Software interface“ “AN86: Ringing / Ringtrip Operation and Architecture on the Si3220/Si3225“ “AN88: Dual ProSLIC Line Card Design“ “AN91: Si3200 Power Offload Circuit“ “AN196: Dual ProSLIC Digital Impedance Synthesis” Si3220PPT0-EVB Data Sheet Si3225PPT0-EVB Data Sheet Note: Refer to www ...
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Related Parts Part Number Si3210 Programmable CMOS SLIC/codec with Ringing/Battery Voltage Generation Si3216 Programmable Wideband CMOS SLIC/ codec with Ringing/Battery Voltage Gener- ation Si3232 Dual CMOS Programmable SLICs with Line Monitoring Si3050/Si3019 Global Voice/Data DAA Si2456/Si2433/ ISOmodem™ with Integrated Global ...
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... Modified PTHxx and PLPFxx examples τ Added value for for Si3200 thermal Table 21 on page 39 Added PTH12 range and resolution for Si3200 mode Modified PSUM range and resolution Modified bit range for PLPF12-PLPF56 "Loop Closure Detection" on page 42 Modified equation for LCRLPF "Ground Key Detection" on page 43 ...
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... Added resistors R20, R21, R22, R23, R24 and 25 Figure 13, “Si3225 Application Circuit Using Centralized Ringer and Secondary Battery Supply,” on page 26: Added resistors R23, R24, R25, R26, R27 and R28. Table 15, “Si3220 + Si3200 External Component Values,” on page 27 Added resistors R20–R25. Si3220/Si3225 Table 16, “Si3225 + Si3200 External Component Values,” ...
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