AD9642BCPZ-170 Analog Devices Inc, AD9642BCPZ-170 Datasheet
AD9642BCPZ-170
Specifications of AD9642BCPZ-170
Related parts for AD9642BCPZ-170
AD9642BCPZ-170 Summary of contents
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FEATURES SNR = 71.0 dBFS at 185 MHz A and 250 MSPS IN SFDR = 83 dBc at 185 MHz A and 250 MSPS IN −152.0 dBFS/Hz input noise at 200 MHz, −1 dBFS A Total power consumption: 390 mW ...
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AD9642 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 ADC DC Specifications ............................................................... 3 ADC AC Specifications ............................................................... 4 Digital Specifications ...
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SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, unless otherwise noted. Table 1. Parameter Temperature RESOLUTION Full ACCURACY No ...
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AD9642 ADC AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR ...
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Parameter 2 FULL POWER BANDWIDTH NOISE BANDWIDTH 3 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Full power bandwidth is the bandwidth of operation where typical ADC ...
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AD9642 SWITCHING SPECIFICATIONS Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate 1 Conversion Rate CLK Period—Divide-by-1 Mode (t ) CLK CLK Pulse Width High ( Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode, DCS Disabled Divide-by-2 Mode Through Divide-by-8 ...
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TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments SPI TIMING REQUIREMENTS See Figure 58 for SPI timing diagram t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge ...
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AD9642 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND VIN+, VIN− to AGND CLK+, CLK− to AGND VCM to AGND CSB to AGND SCLK to AGND SDIO to AGND D0−/D1−, D0+/D1+ Through D12−/D13−, D12+/D13+ to ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 8. Pin Function Descriptions Pin No. Mnemonic ADC Power Supplies 8, 17 DRVDD 3, 27, 28, 31, 32 AVDD 0 AGND, Exposed Paddle 25 DNC ADC Analog 30 VIN+ 29 VIN− 26 VCM 1 ...
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AD9642 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum rate per speed grade, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample 25°C, unless otherwise noted. A ...
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SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 INPUT AMPLITUDE (dBFS) Figure 10. AD9642-170 Two-Tone SFDR/IMD3 vs. Input Amplitude ( ...
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AD9642 0 210MSPS 90.1MHz @ –1dBFS –20 SNR = 71.2dB (72.2dBFS) SFDR = 92dBc –40 –60 THIRD HARMONIC –80 SECOND HARMONIC –100 –120 –140 FREQUENCY (MHz) Figure 16. AD9642-210 Single-Tone FFT with f 0 210MSPS ...
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SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 INPUT AMPLITUDE (dBFS) Figure 22. AD9642-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (A with f ...
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AD9642 0 250MSPS 90.1MHz @ –1dBFS –20 SNR = 71dB (72dBFS) SFDR = 89dBc –40 THIRD HARMONIC –60 SECOND HARMONIC –80 –100 –120 –140 FREQUENCY (MHz) Figure 28. AD9642-250 Single-Tone FFT with f 0 250MSPS 185.1MHz ...
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SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 INPUT AMPLITUDE (dBFS) Figure 34. AD9642-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (A with f ...
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AD9642 EQUIVALENT CIRCUITS AVDD VIN Figure 40. Equivalent Analog Input Circuit AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 41. Equivalent Clock Input Circuit DRVDD V+ V– DATAOUT– DATAOUT+ V– V+ Figure 42. Equivalent LVDS Output Circuit AVDD CLK– Rev. 0 ...
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THEORY OF OPERATION The AD9642 can sample any f /2 frequency segment from 250 MHz using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Programming and control of the AD9642 ...
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AD9642 For baseband applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 48. To bias the analog input, connect the VCM voltage to the center tap of the ...
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VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9642. The full-scale input range can be adjusted by varying the reference voltage via SPI. The input span of the ADC tracks reference voltage changes linearly. CLOCK INPUT ...
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AD9642 cycle control loop does not function for clock rates less than 40 MHz nominally. The loop has a time constant associated with it that must be considered when the clock rate may change dynamically. A wait time of 1.5 ...
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Timing The AD9642 provides latched data with a pipeline delay of 10 input sample clock cycles. Data outputs are available one propagation delay (t ) after the rising edge of the clock signal. PD Minimize the length of the output ...
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AD9642 SERIAL PORT INTERFACE (SPI) The AD9642 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI offers added flexibility and customization, depending ...
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SPI ACCESSIBLE FEATURES Table 12 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Table 12. Features ...
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AD9642 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02); the ...
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MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 13 are not currently supported for this device. Table 13. Memory Map Registers Addr Register Bit 7 (Hex) Name (MSB) Bit 6 Chip Configuration Registers ...
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AD9642 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x0E BIST enable Open Open 0x10 Offset adjust Open Open 0x14 Output mode Open Open 0x15 Output adjust Open Open 0x16 Clock phase Invert Open control DCO clock 0x17 DCO ...
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APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting system level design and layout of the AD9642 recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements for certain pins. Power and Ground ...
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... PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9642BCPZ-170 −40°C to +85°C AD9642BCPZ-210 −40°C to +85°C AD9642BCPZ-250 −40°C to +85°C AD9642BCPZRL7-170 −40°C to +85°C AD9642BCPZRL7-210 −40°C to +85°C AD9642BCPZRL7-250 −40°C to +85°C AD9642-170EBZ − ...