A54SX32-2BG329IX3 MICROSEMI, A54SX32-2BG329IX3 Datasheet - Page 33

• Manufacturer Part Number: A54SX32-2BG329IX3
• Manufacturer: MICROSEMI

Specifications of A54SX32-2BG329IX3

• Lead Free Status / Rohs Status: Not Compliant

Table 1-19 • A54SX16P Timing Characteristics (Continued)
Parameter
Dedicated (Hardwired) Array Clock Network
t
t
t
t
t
t
f
Routed Array Clock Networks
t
t
t
t
t
t
t
t
t
t
t
TTL Output Module Timing
t
t
t
t
t
t
Note:
1. For dual-module macros, use t
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
3. Delays based on 10 pF loading.
HCKH
HCKL
HPWH
HPWL
HCKSW
HP
HMAX
RCKH
RCKL
RCKH
RCKL
RCKH
RCKL
RPWH
RPWL
RCKSW
RCKSW
RCKSW
DLH
DHL
ENZL
ENZH
ENLZ
ENHZ
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
(Worst-Case Commercial Conditions, V
Description
Input LOW to HIGH (pad to R-Cell input)
Input HIGH to LOW (pad to R-Cell input)
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
Minimum Period
Maximum Frequency
Input LOW to HIGH (light load)
(pad to R-Cell input)
Input HIGH to LOW (Light Load)
(pad to R-Cell input)
Input LOW to HIGH (50% load)
(pad to R-Cell input)
Input HIGH to LOW (50% load)
(pad to R-Cell input)
Input LOW to HIGH (100% load)
(pad to R-Cell input)
Input HIGH to LOW (100% load)
(pad to R-Cell input)
Min. Pulse Width HIGH
Min. Pulse Width LOW
Maximum Skew (light load)
Maximum Skew (50% load)
Maximum Skew (100% load)
Data-to-Pad LOW to HIGH
Data-to-Pad HIGH to LOW
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
PD
+ t
RD1
+ t
PDn
, t
RCO
+ t
CCR
Min.
RD1
'–3' Speed
1.4
2.7
2.1
1.4
2.1
= 4.75 V, V
+ t
v3.2
PDn,
Max.
350
1.2
1.2
0.2
1.6
1.8
1.8
2.0
1.8
2.0
0.5
0.5
0.5
2.4
2.3
3.0
3.3
2.3
2.8
or t
CCA
PD1
Min.
,V
'–2' Speed
1.6
1.6
3.1
2.4
2.4
+ t
CCI
RD1
= 3.0 V, T
Max.
+ t
320
1.4
1.4
0.2
1.8
2.0
2.1
2.2
2.1
2.2
2.8
2.7
0.5
0.6
0.6
2.9
3.4
3.8
3.2
SUD
, whichever is appropriate.
J
Min.
= 70°C)
'–1' Speed
1.8
1.8
3.6
2.7
2.7
Max.
280
1.5
1.6
0.3
2.1
2.3
2.5
2.5
2.4
2.5
0.5
0.7
0.7
3.1
3.2
3.9
4.3
3.0
3.7
Min.
'Std' Speed
2.1
2.1
4.2
3.2
3.2
SX Family FPGAs
Max.
240
1.8
1.9
0.3
2.5
2.7
2.8
3.0
2.8
3.0
0.7
0.8
0.8
3.7
3.8
4.6
5.0
3.5
4.3
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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