A54SX32 Actel Corporation, A54SX32 Datasheet
A54SX32
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A54SX32 Summary of contents
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... See the Actel website for the latest version of the datasheet. v3.2 ™ A54SX16P A54SX32 16,000 32,000 24,000 48,000 1,452 2,880 924 1,800 528 1,080 175 249 3 3 Yes Yes Yes – ...
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... Ordering Information P 2 A54SX16 – Blank = Not PCI Compliant P = PCI Compliant Part Number A54SX08 = 12,000 System Gates A54SX16 = 24,000 System Gates A54SX16P = 24,000 System Gates A54SX32 = 48,000 System Gates Plastic Device Resources PLCC Device 84-Pin A54SX08 69 A54SX16 – A54SX16P – A54SX32 – ...
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Table of Contents SX Family FPGAs General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SX Family FPGAs General Description The Actel SX family of FPGAs features a sea-of-modules architecture that delivers device performance and integration levels not currently achieved by any other FPGA architecture. SX devices greatly simplify design time, enable dramatic reductions in ...
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SX Family FPGAs The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable (using the S0 and S1 lines) control signals (Figure registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional Routing Tracks ...
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Chip Architecture The SX family chip architecture provides a unique approach to module organization and chip routing that delivers the best register/logic mix for a wide variety of new and emerging applications. Module Organization Actel has arranged all C-cell and ...
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SX Family FPGAs Routing Resources Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within clusters and SuperClusters (Figure 1-5 of ...
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... Table 1-1 • Supply Voltages Device V V CCA A54SX08 3.3 V 3.3 V A54SX16 A54SX32 A54SX16-P* 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 5.0 V Note: *A54SX16-P has three different entries because it is capable of both a 3.3 V and a 5.0 V drive. Performance The combination of architectural features described ...
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SX Family FPGAs Boundary Scan Testing (BST) All SX devices are IEEE 1149.1 compliant. SX devices offer superior diagnostic and testing capabilities by providing Boundary Scan Testing (BST) and probing capabilities. These functions are controlled through the special test pins ...
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... Operating Conditions Table 1-3 • Absolute Maximum Ratings Symbol Supply Voltage CCR Supply Voltage CCA Supply Voltage (A54SX08, A54SX16, A54SX32) CCI Supply Voltage (A54SX16P) CCI V Input Voltage I V Output Voltage O I I/O Source Sink Current IO T ...
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SX Family FPGAs Table 1-4 • Recommended Operating Conditions Parameter Temperature Range* 3.3 V Power Supply Tolerance 5.0 V Power Supply Tolerance Note: *Ambient temperature ( used for commercial and industrial; case temperature (T A Table 1-5 • ...
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PCI Compliance for the SX Family The SX family supports 3.3 V and 5.0 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1. Table 1-6 • A54SX16P DC Specifications (5.0 V PCI Operation) Symbol Parameter V ...
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SX Family FPGAs A54SX16P AC Specifications for (PCI Operation) Table 1-7 • A54SX16P AC Specifications for (PCI Operation) Symbol Parameter I Switching Current High OH(AC) (Test Point) I Switching Current High OL(AC) (Test Point) I Low Clamp Current CL slew ...
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Figure 1-9 shows the 5.0 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P device. 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 –0.05 PCI I Mininum OH –0.10 –0.15 –0.20 ...
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SX Family FPGAs A54SX16P DC Specifications (3.3 V PCI Operation) Table 1-8 • A54SX16P DC Specifications (3.3 V PCI Operation) Symbol Parameter V Supply Voltage for Array CCA V Supply Voltage required for Internal Biasing CCR V Supply Voltage for ...
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A54SX16P AC Specifications (3.3 V PCI Operation) Table 1-9 • A54SX16P AC Specifications (3.3 V PCI Operation) Symbol Parameter Condition Switching Current High 0 < V 0.3V I OH(AC) 0.7V (Test Point) V Switching Current High V 0.6V I OL(AC) ...
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SX Family FPGAs Figure 1-10 shows the 3.3 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P device. 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0. –0.05 PCI I Minimum ...
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... V 3.3 V 5.0 V 3.3 V 5.0 V Note: No inputs should be driven (high or low) before completion of power-up. Power-Down Sequencing Table 1-11 • Power-Down Sequencing V V CCA CCR A54SX08, A54SX16, A54SX32 3.3 V 5.0 V A54SX16P 3.3 V 3.3 V 3.3 V 5.0 V 3.3 V 5.0 V Note: No inputs should be driven (high or low) after the beginning of the power-down sequence. V Power-Up Sequence CCI 3 ...
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SX Family FPGAs Evaluating Power in SX Devices A critical element of system reliability is the ability of electronic devices to safely dissipate the heat generated during operation. The thermal characteristics of a circuit depend on the device and package ...
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... P Total AC DC Guidelines for Calculating Power values for various Consumption The power consumption guidelines are meant to A54SX16P A54SX32 represent worst-case scenarios so that they can be generally used to predict the upper limits of power 4.0 4.0 dissipation. These guidelines are shown in 3.4 3.4 Sample Power Calculation 4.7 4 ...
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SX Family FPGAs Step 1: Define Terms Used in Formula Module Number of logic modules switching at f (Used 50%) m Average logic modules switching rate f (MHz) (Guidelines: f/10) m Module capacitance C (pF) EQM Input Buffer Number of ...
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Figure 1-11 shows the characterized power dissipation numbers for the shift register design using frequencies ranging from 1 MHz to 200 MHz. 1200 1000 800 600 400 200 Figure 1-11 • Power Dissipation Junction Temperature (T ) ...
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SX Family FPGAs Table 1-15 • Package Thermal Characteristics Package Type Plastic Leaded Chip Carrier (PLCC) Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP) Very Thin Quad Flatpack (VQFP) Plastic Quad Flat Pack (PQFP) without Heat Spreader Plastic ...
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SX Timing Model Input Delays I/O Module t = 1.5 ns INY t = 0.5 ns SUD Routed Clock t = 1.5 ns (100% Load) RCKH F = 250 MHz MAX Hardwired Clock t = ...
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SX Family FPGAs GND 50% 50 Out 1 DLH DHL Figure 1-13 • Output Buffer Delays Load 1 (used to measure propagation delay) To Output Under Test 35 pF Figure ...
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Register Cell Timing Characteristics D t SUD CLK Q CLR PRESET Figure 1-17 • Flip-Flops Timing Characteristics Timing characteristics for SX devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input characteristics are common to all SX family members. ...
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SX Family FPGAs A54SX08 Timing Characteristics Table 1-17 • A54SX08 Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect DC ...
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Table 1-17 • A54SX08 Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description Dedicated (Hardwired) Array Clock Network t Input LOW to HIGH (pad to R-Cell input) HCKH t Input HIGH to LOW (pad to R-Cell input) HCKL t Minimum ...
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SX Family FPGAs A54SX16 Timing Characteristics Table 1-18 • A54SX16 Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect DC ...
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Table 1-18 • A54SX16 Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description Dedicated (Hardwired) Array Clock Network t Input LOW to HIGH (pad to R-Cell input) HCKH t Input HIGH to LOW (pad to R-Cell input) HCKL t Minimum ...
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SX Family FPGAs A54SX16P Timing Characteristics Table 1-19 • A54SX16P Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect DC ...
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Table 1-19 • A54SX16P Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description Dedicated (Hardwired) Array Clock Network t Input LOW to HIGH (pad to R-Cell input) HCKH t Input HIGH to LOW (pad to R-Cell input) HCKL t Minimum ...
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SX Family FPGAs Table 1-19 • A54SX16P Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description TTL/PCI Output Module Timing t Data-to-Pad LOW to HIGH DLH t Data-to-Pad HIGH to LOW DHL t Enable-to-Pad ENZL t Enable-to-Pad, ...
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... A54SX32 Timing Characteristics Table 1-20 • A54SX32 Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect Routing Delay, Fast Connect Routing Delay RD1 Routing Delay ...
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... SX Family FPGAs Table 1-20 • A54SX32 Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description Dedicated (Hardwired) Array Clock Network t Input LOW to HIGH (pad to R-Cell input) HCKH t Input HIGH to LOW (pad to R-Cell input) HCKL t Minimum Pulse Width HIGH HPWH t Minimum Pulse Width LOW ...
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Pin Description CLKA/B Clock A and B These pins are 3 5.0 V PCI/TTL clock inputs for clock distribution networks. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set ...
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Package Pin Assignments 84-Pin PLCC Figure 2-1 • 84-Pin PLCC (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html 84-Pin PLCC v3.2 54SX Family FPGAs 2-1 ...
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Family FPGAs 84-Pin PLCC A54SX08 Pin Number Function 1 V CCR 2 GND 3 V CCA 4 PRA, I/O 5 I CCI 8 I/O 9 I/O 10 I/O 11 TCK, I/O 12 TDI, I/O 13 ...
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PQFP 208 1 Figure 2-2 • 208-Pin PQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. 208-Pin PQFP v3.2 54SX Family FPGAs 2-3 ...
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... V CCR CCR 26 GND GND CCA CCA 28 GND GND 29 I/O I/O 30 I/O I I/O 32 I/O I/O 33 I/O I/O 34 I/O I I/O 36 I/O I/O Note: * Note that Pin 65 in the A54SX32—PQ208 connect (NC A54SX32 Function Pin Number GND 37 TDI, I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 TMS CCI CCI I/O 49 I/O 50 I/O 51 I/O 52 ...
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... I/O I/O 102 I/O I/O 103 TDO, I/O TDO, I/O 104 I/O I/O 105 GND GND 106 NC I/O 107 I/O I/O 108 NC I/O Note: * Note that Pin 65 in the A54SX32—PQ208 connect (NC). A54SX32 Function Pin Number I/O 109 I/O 110 I/O 111 PRB, I/O 112 GND 113 V 114 CCA CCA GND 115 V 116 CCR CCR ...
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... I/O I/O 172 I/O I/O 173 NC I/O 174 I/O I/O 175 I/O I/O 176 NC I/O 177 I/O I/O 178 I/O I/O 179 I/O I/O 180 CLKA CLKA Note: * Note that Pin 65 in the A54SX32—PQ208 connect (NC A54SX32 Function Pin Number V 181 CCA GND 182 I/O 183 V 184 CCI CCI I/O 185 I/O 186 I/O 187 I/O 188 I/O 189 I/O 190 I/O 191 ...
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TQFP 144 1 Figure 2-3 • 144-Pin TQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. 144-Pin TQFP v3.2 54SX Family FPGAs 2-7 ...
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... CCI CCI GND 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I CCR CCR V 56 CCA CCA I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 GND CCI CCI V 66 CCA CCA I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 GND 72 v3.2 144-Pin TQFP A54SX08 A54SX16P A54SX32 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I CCI CCI CCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O PRB, I/O PRB, I/O I/O I/O I ...
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... CCR I/O 127 V I/O 128 GND I/O 129 V I/O 130 I/O 131 PRA, I/O I/O 132 I/O 133 V 134 CCA GND 135 I/O 136 GND 137 V 138 CCI I/O 139 I/O 140 I/O 141 I/O 142 I/O 143 I/O 144 TCK, I/O v3.2 54SX Family FPGAs 144-Pin TQFP A54SX16P A54SX32 Function Function GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I CCI CCI CCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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Family FPGAs 176-Pin TQFP 176 1 Figure 2-4 • 176-Pin TQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html 176-Pin TQFP v3.2 ...
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... I/O 41 I/O 42 I/O 43 TMS CCI I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 GND CCA GND 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 I/O 64 PRB, I/O I CCI V 67 CCA I/O 68 v3.2 54SX Family FPGAs 176-Pin TQFP A54SX16, A54SX16P A54SX32 Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I CCI CCI CCI I/O I/O I/O NC I/O I/O I/O I/O ...
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... TDO, I/O 121 I/O 122 GND 123 I/O 124 I/O 125 I/O 126 I/O 127 I/O 128 I/O 129 I/O 130 I/O 131 V 132 CCA V 133 CCI CCI I/O 134 I/O 135 I/O 136 v3.2 176-Pin TQFP A54SX16, A54SX08 A54SX16P A54SX32 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND CCA CCA CCA GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... V 160 CCI I/O 161 I/O 162 I/O 163 I/O 164 I/O 165 I/O 166 I/O 167 I/O 168 I/O 169 I/O 170 I/O 171 CLKA 172 CLKB 173 V 174 CCR GND 175 V 176 TCK, I/O CCA v3.2 54SX Family FPGAs 176-Pin TQFP A54SX16, A54SX16P A54SX32 Function Function PRA, I/O PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I CCI CCI CCI ...
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Family FPGAs 100-Pin VQFP 100 1 Figure 2-5 • 100-Pin VQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html 100-Pin VQFP v3.2 ...
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VQFP A54SX16, Pin A54SX08 A54SX16P Number Function Function 1 GND GND 2 TDI, I/O TDI, I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 TMS TMS CCI CCI 9 GND GND ...
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Family FPGAs 313-Pin PBGA ...
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... D16 I/O V D18 I/O CCA I/O D20 I/O I/O D22 I/O I/O D24 NC I/O E1 I/O TDO, I GND E5 I/O TCK, I/O E7 I/O I/O E9 I/O I/O E11 I/O I/O E13 V CCA v3.2 54SX Family FPGAs 313-Pin PBGA Pin A54SX32 Number Function E15 I/O E17 I/O E19 I/O E21 I/O E23 I/O E25 I/O F2 I I/O F10 NC F12 I/O F14 I/O F16 NC F18 I/O F20 I/O F22 I/O F24 I/O G1 I/O G3 ...
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... P6 I/O U11 P8 I/O U13 P10 I/O U15 P12 GND U17 P14 GND U19 P16 I/O U21 P18 I/O U23 P20 NC U25 P22 I/O V2 P24 I I I/O V8 v3.2 313-Pin PBGA A54SX32 Pin A54SX32 Function Number Function I/O V10 I/O I/O V12 I/O I/O V14 I/O I/O V16 NC GND V18 I/O I/O V20 I/O I/O V22 V CCA I/O V24 V CCI I/O W1 I/O I/O W3 I/O I/O W5 I/O I/O W7 ...
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PBGA Figure 2-7 • 329-Pin PBGA (Top View) Note For Package Manufacturing and ...
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... AC20 AB9 I/O AC21 I/O AC22 PRB, I/O AC23 I/O B1 HCLK B2 I/O B3 I/O B4 I/O B5 I/O B6 I/O B7 I/O B8 I/O B9 I/O B10 GND B11 I/O B12 AC1 GND B13 v3.2 329-Pin PBGA A54SX32 Pin A54SX32 Function Number Function V B14 I/O CCI NC B15 I/O I/O B16 I/O I/O B17 I/O I/O B18 I/O I/O B19 I/O I/O B20 I/O V B21 I/O CCI I/O B22 GND I/O B23 V CCI I ...
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... M20 V CCA I/O M21 I/O I/O M22 I/O I/O M23 V CCI GND N1 I/O GND N2 I/O GND N3 I/O GND N4 I/O GND N10 GND v3.2 54SX Family FPGAs 329-Pin PBGA Pin A54SX32 Number Function N11 GND N12 GND N13 GND N14 GND N20 NC N21 I/O N22 I/O N23 I/O P1 I/O P2 I/O P3 I/O P4 I/O P10 GND P11 GND P12 ...
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... Pin Function Number V4 I/O W23 V20 I/O Y1 V21 I/O Y2 V22 I/O Y3 V23 I/O Y8 W20 I/O Y9 W21 I/O Y10 W22 I/O Y11 v3.2 329-Pin PBGA A54SX32 Pin A54SX32 Function Number Function NC Y12 V CCA NC Y13 V CCR I/O Y14 I/O I/O Y15 I/O GND Y16 I/O I/O Y17 I/O I/O Y18 I/O I/O Y19 I/O I/O Y20 GND I/O Y21 I/O I/O Y22 I/O I/O Y23 I/O ...
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FBGA Figure 2-8 • 144-Pin FBGA (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html ...
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Family FPGAs 144-Pin FBGA Pin A54SX08 Number Function Number A1 I/O A2 I/O A3 I CCA A6 GND A7 CLKA A8 I/O A9 I/O A10 I/O A11 I/O A12 I/O B1 I/O B2 GND B3 ...
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... Information concerning the TRST pin in the The "Dedicated Test Mode" section The "Programming" section A note was added to the A note was added to the following devices: A54SX08, A54SX16, A54SX32. U11 and U13 were added to the v3.0.1 Storage temperature in Table 1-1 was updated. Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as " ...
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