PPC440EPX-NUA667T Applied Micro Circuits Corporation, PPC440EPX-NUA667T Datasheet - Page 89

• Manufacturer Part Number: PPC440EPX-NUA667T
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440EPX-NUA667T

• Family Name: 440EPx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/3.3V
• Operating Supply Voltage (max): 1.6/3.45V
• Operating Supply Voltage (min): 1.425/3.15V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 680
• Package Type: TEBGA
• Lead Free Status / Rohs Status: Compliant

Revision 1.30 – February 27, 2009
Boot Configuration
The PPC440EPx supports several configurable boot parameters that must be initialized prior to booting. These
parameters are configured by one of several default boot options or programmed by data read from an IIC serial
EEPROM (see “Serial EEPROM” below). Strap signals sampled during reset select which method is used to
initialize the boot parameters (see “Strapping” below).
Strapping
The Bootstrap Controller selects the boot options based on the state of the strap signals during reset. The strap
signals are sampled on the rising edge of SysClk while SysReset(overbar) is driven low. They must not change
state until after SysReset(overbar) is driven high in order to guarantee the correct boot option is selected.
These pins are used for strap functions only during reset. Following reset, they are used for normal functions. The
signal names assigned to the pins for normal operation are shown in parentheses following the pin number.
Note:
select.
The following table lists the strapping pins along with their functions and boot strap options:
Serial EEPROM
Boot Options G and H enable the Bootstrap Controller to read 16 bytes of configuration data from a serial
EEPROM attached to the IIC0 bus after SysReset(overbar) de-asserts. The Bootstrap Controller stores the data in
the SDR0_SDSTP0:3 registers.
Note:
The initialization settings and their default values are covered in detail in the PowerPC 440EPx/GRx Embedded
Processor User’s Manual.
AMCC Proprietary
Table 28. Strapping Pin Assignments
Data Sheet
1. Bootstrap options A, B, D, and E result in a PLL Forward Divisor B setting such that Forward Divisor B output frequency exceeds the CPU
Serial device is disabled. Each of the six options (A–
F) is a combination of boot source, boot-source
width, and clock frequency specifications. Refer to
the IIC Bootstrap Controller chapter in the
PPC440EPx Embedded Processor User’s Manual
for details.
Serial device is enabled. The option being selected is
the IIC0 slave address that will respond with
strapping data.
clock frequency. Following a power up, system reset or chip reset (when CPR0_ICFG[RLI] = 0), FWDVB and PRBDV0 must be re-
programmed as documented in the PowerPC 440EPx/GRx Embedded Processor User’s Manual in the Bootstrap Options section. The
dividers must be re-programmed before the DDR is tuned such that the output of PLL Forward Divider B does not exceed the CPU clock
frequency.
To isolate the strapping pins, the ExReset(overbar) signal may be used as a buffer enable or multiplexer
The IIC serial EEPROM must have a one-byte base address. Multi-byte base addresses are not supported.
Function
G (0xA8)
H (0xA4)
Option
A
B
D
E
C
F
1
1
1
1
440EPx – PPC440EPx Embedded Processor
(UART0_DCD)
C28
0
0
0
0
1
1
1
1
(UART0_DSR)
Pin Strapping
C29
0
0
1
1
0
1
0
1
(UART0_CTS)
A29
0
1
0
1
0
0
1
1
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