UPD8891CY NEC, UPD8891CY Datasheet
UPD8891CY
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UPD8891CY Summary of contents
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... The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S16039EJ2V0DS00 (2nd edition) ...
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BLOCK DIAGRAM φ V GND GND OUT 20 (Blue OUT 21 (Green OUT 2 (Red φ φ φ 1L CLB SEL 2 φ ...
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... Shift register clock 2 φ 2-1200 (for 1200 dpi) Shift register clock 1 φ 1-1200 (for 1200 dpi) φ Transfer gate clock 3 (for Red) TG3 φ Transfer gate clock 2 (for Green) TG2 Ground GND Caution Connect the No connection pins (NC) to GND OUT OUT φ ...
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PHOTOCELL STRUCTURE DIAGRAM 1200 dpi sensor µ µ m 2.75 m 2.5 Aluminium shield PHOTOCELL ARRAY STRUCTURE DIAGRAM 1 (Line Spacing) 10.5 µ m 10.5 µ 300 dpi sensor m 10.5 µ m 5.25 µ m 5.25 µ m 5.25 ...
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PHOTOCELL ARRAY STRUCTURE DIAGRAM 2 (The Relation of the Photocell Array) Dummy Optical black 46 pixels 100 pixels 1-45 47-145 1200 dpi 2-46 48-146 12 pixels 25 pixels 300 dpi 1-12 13-37 Invalid photocell Valid photocell 8 pixels 10680 pixels ...
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ABSOLUTE MAXIMUM RATINGS (T Parameter Output drain voltage V OD Shift register clock voltage V φ 1-300 V φ 2-300 Reset gate clock voltage V φ RB Reset feed-through level clamp V φ CLB clock voltage 300/1200 dpi select signal ...
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ELECTRICAL CHARACTERISTICS = +25° data rate (f φ light source : 3200 K halogen lamp + C-500S (infrared cut filter mm) + HA-50 (heat absorbing filter ...
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INPUT PIN CAPACITANCE ( 25° ° ° ° Parameter Shift register clock pin capacitance 1 Shift register clock pin capacitance 2 Last stage sift reset gate clock pin capacitance 1 Last stage ...
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TIMING CHART 1− − − − 1 (1200 dpi, for each color) φ φ TG1 to TG3 φ φ 1-1200, 1L φ φ 2-1200, 2L φ RB Note φ CLB (Bit clamp mode) φ CLB (Line clamp mode ...
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TIMING CHART 1− − − − 2 (600 dpi, even pixel, for each color) φ φ TG1 to TG3 φ φ 1-1200, 1L φ φ 2-1200, 2L φ RB Note φ CLB (Bit clamp mode) φ CLB (Line clamp mode) ...
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TIMING CHART 1− − − − 3 (600 dpi, odd pixel, for each color) φ φ TG1 to TG3 φ φ 1-1200, 1L φ φ 2-1200, 2L φ RB Note φ CLB (Bit clamp mode) φ CLB (Line clamp mode) ...
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TIMING CHART 1− − − − 4 (300 dpi, for each color) φ φ TG1 to TG3 φ φ 1-300, 1L φ φ 2-300, 2L φ RB Note φ CLB (Bit clamp mode) φ CLB (Line clamp mode ...
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TIMING CHART 2− − − − 1 (1200 dpi, bit clamp mode, for each color) φ 1-1200 φ 2-1200 φ 1L φ 90% φ 90% φ CLB 10% + RFTN RFTN ...
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TIMING CHART 2− − − − 2 (1200 dpi, line clamp mode, for each color) φ 1-1200 φ 2-1200 φ 1L φ 90% φ RB 10% “H” φ CLB + RFTN RFTN – V OUT Symbol ...
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TIMING CHART 2− − − − 3 (600 dpi, even pixel, bit clamp mode, for each color) t1 φ 1-1200 φ 2-1200 t1’ φ 1L φ t3’ t3’ 90% φ 90% φ ...
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TIMING CHART 2− − − − 4 (600 dpi, even pixel, line clamp mode, for each color) t1 φ 1-1200 φ 2-1200 t1’ φ 1L φ t3’ t3’ 90% φ RB 10% “H” φ CLB + RFTN ...
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TIMING CHART 2− − − − 5 (600 dpi, odd pixel, bit clamp mode, for each color) φ 1-1200 φ 2-1200 φ 1L φ 2L φ RB φ CLB V OUT Symbol t1, t2 t1’, t2’ t3’ t4 t5, t6 ...
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TIMING CHART 2− − − − 6 (600 dpi, odd pixel, line clamp mode, for each color) φ 1-1200 φ 2-1200 φ 1L φ 2L φ RB “H” φ CLB V OUT Symbol t1, t2 t1’, t2’ t3’ t4 t5, ...
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TIMING CHART 2− − − − 7 (300 dpi, bit clamp mode, for each color) φ 1-300 φ 2-300 φ 1L φ 90% φ 90% φ CLB 10% + RFTN RFTN ...
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TIMING CHART 2− − − − 8 (300 dpi, line clamp mode, for each color) φ 1-300 φ 2-300 φ 1L φ 90% φ RB 10% “H” φ CLB + RFTN RFTN – V OUT Symbol ...
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TG1 to φ φ φ φ TG3, φ φ φ φ 1, φ φ φ φ 2 TIMING CHART φ φ TG1 to TG3 90% φ φ 1-300, 1-1200 φ φ 2-300, 2-1200 φ RB φ ...
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φ φ φ φ 1-300, φ φ φ φ 2-300 cross points φ 1-300 φ 2-300 φ φ φ φ 1-1200, φ φ φ φ 2-1200 cross points φ 1-1200 φ 2-1200 φ φ φ φ 1-300, φ φ φ ...
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DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : V sat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage ...
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Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : ...
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Register Imbalance : RI (1200 dpi) The rate of the difference between the averages of the output voltage of Odd and Even bits, against the average output voltage of all the valid pixels ∑ – ...
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STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC 0.5 0.25 0 Operating Ambient Temperature T TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter ) (T 100 ...
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... Caution Connect the No connection pins (NC) to GND. Remarks 1. The inverters shown in the above application circuit example are the 74HC04 (data rate < 2 MHz) or the 74AC04 (2 ≤ data rate < 5 MHz the application circuit example are shown in the figure blow. ...
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PACKAGE DRAWING µ PD8891CY CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400) ) (Unit : mm) 44.0±0.3 1st valid pixel 1 0.5±0 37.5 1.02±0.15 0.46±0.1 2.54±0.25 28 9.25±0 2.0 (1.72) 4.39±0.4 2.62±0.2 (5.42) 4.21±0.5 ...
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RECOMMENDED SOLDERING CONDITIONS When soldering this product highly recommended to observe the conditions as shown below. If other soldering processes are used the soldering is performed under different conditions, please make sure to consult with our ...
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... For the shipment of mounted substrates, use box treated for prevention of static charges. 6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 MΩ. 30 Solvents ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • ...