BT8222EPFE Conexant Systems, Inc., BT8222EPFE Datasheet

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BT8222EPFE

Manufacturer Part Number
BT8222EPFE
Description
ATM transmitter/receiver with UTOPIA interface
Manufacturer
Conexant Systems, Inc.
Datasheet
CN8223
ATM Transmitter/Receiver with UTOPIA Interface
The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a
single-access ATM service termination for User-to-Network (UNI) and
Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI
Specification 94/0317; Bellcore Specifications TR-TSV-000772, TR-TSV-000773,
TR-NWT-000253, and T1S1/92-185; ITU Recommendations I.432, G.707, G.751,
G.832, and Q.921; and ETSI prETS 300 213 and 300 214. Both Customer Premise
Equipment (CPE) and switching system interface functions are provided. The CN8223
provides DS1, E1, DS3, E3, E4, STS-1, and STS-3c (and STM-1) ATM cell alignment
functions. The system interface is via a parallel FIFO port or UTOPIA interface. In
addition, the CN8223 terminates the operations and maintenance flows F1, F2, and F3.
receiver port can be programmed with a particular Virtual Channel Identifier/Virtual
Path Identifier (VCI/VPI) address for message routing. VCI/VPI pages can also be
selected via masking registers.
by the transmitter on an individual port basis. The microprocessor can also control
insertion of all overhead and can insert errors in selected fields for test equipment
applications.
Functional Block Diagram
Data Sheet
Control
Interface
UTOPIA
or FIFO
Data
Port
Bus
The CN8223 provides four FIFO port interfaces and one UTOPIA interface. Each
The microprocessor can set control registers for insertion of selected header fields
8
8
FIFO
Cell
8
Generation
Header
Filter
Interface
Cell
4-Port
FIFO
8
ATM Layer
Microprocessor
Validation
Control
Address
Rate
Cell
TX
7
52 Control Registers
28 Status Registors
Microprocessor
Interface
8
8
Microprocessor
Alignment
8
HEC or
Data
PLCP
Cell
16
Physical Framing
E3 (G.751)
E3 (G.832)
E4 (G.832)
HDLC
Framers
STS-3c
Data
Link
STM-1
Line Overhead
STS-1
TAXI
DS3
8
8
1
1
ATM
UNI
Distinguishing Features
• Integrates 7 line framers with ATM
• UTOPIA Level 1 interface
• Internal framers for DS3, E3 (G.751,
• PLCP and G.804 HEC cell alignment
• Direct interface to TAXI
• ATM and SMDS cell modes
• 4 FIFO ports with header screening,
• Idle cells generated and screened
• Statistics counts latched on
• Error detection and insertion
• Option insertion or generation of all
• Serial or parallel line interface
• Available evaluation module
• Supports Automatic Protection
Applications
• WAN equipment
• ATM switches
• Test equipment
• ATM routers and hub
layer processing according to ATM
Forum UNI and NNI Specifications
G.832), E4 (G.832), STS-1, STS-3c,
STM-1
for all data rates from 1.544 Mbps to
155 Mbps
T1/E1 framers
formatting, and transmit priority
controls
one-second intervals
line and cell overhead
reference design and software
Switching (APS)
March 8, 2000
TM
or external
100046C

Related parts for BT8222EPFE

BT8222EPFE Summary of contents

Page 1

CN8223 ATM Transmitter/Receiver with UTOPIA Interface The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network (UNI) and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI Specification 94/0317; Bellcore Specifications ...

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... Ordering Information Generic Part Part Number Number 28222-13 Bt8222EPFE 28222-14 Bt8222EPFF 28233-11 CN8223EPF © 1999, 2000, Conexant Systems, Inc. All Rights Reserved. Information in this document is provided in connection with Conexant Systems, Inc. (“Conexant”) products. These materials are provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no responsibility for errors or omissions in these materials ...

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Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 2.0 Functional Description 2.1 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface FIFO Port/UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents Receive Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface List of Figures Figure 1-1. CN8223 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Figures Figure 4-6. FIFO Port Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface List of Tables Table 1-1. CN8223 Version Descriptions ...

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List of Tables Table 3-10. HDR_MSKx Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 11

Product Description The CN8223 ATM Physical Interface (PHY) device is a transmitter/receiver which converts several types of frames to ATM cells and vice versa. The device contains framers for DS3, E3, E4, STS-1, STS-3c, and STM-1. This chapter provides ...

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Product Description 1.1 Block Diagram Figure 1-1. CN8223 Detailed Block Diagram TCLKO_HS ± Line Interfaces ± TXOUT_HS Tx TXCKI_HS ± High HDLC Speed ± RXCKI_HS ± RXIN_HS DS3, E3, E4, STS-1 STS-3c, STM-1 TCLKO Medium Speed TXOUT Transmit Framer ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 1.2 CN8223 Features The CN8223 ATM Transmitter/Receiver provides a single-access ATM service termination for UNI and NNI. It conforms to the following specifications and recommendations: • ATM Forum UNI Specification 94/0317 • Bellcore Specifications ...

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Product Description 1.2 CN8223 Features 1.2.3 Programmable Parity Protection Programmable parity protection is available on the system interface. Read and write strobes allow addressing four distinct data sources and output to four distinct destinations. Each transmitter ...

Page 15

CN8223 ATM Transmitter/Receiver with UTOPIA Interface 1.3 Line Framing Functions The CN8223 provides framers for DS3, E3 (both G.751 and G.832), E4 (G.832), STS-1, and STS-3c/STM-1 formatted serial streams. The line receive circuitry recovers the frame location from the serial ...

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Product Description 1.3 Line Framing Functions 1.3.1 Interfaces The CN8223 has a serial external framer interface for T1, E1, T3, and E3. The internal B3ZS/HDB3 encoder/decoder can be bypassed in any mode for direct input/output of NRZ data and ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 1.3.3 BIP-8 Code The octet Bit Interleaved Parity (BIP-8) code is checked and error status generated for the Far End Block Error (FEBE) function and yellow alarm. BIP-8 code violations and framing-octet errors are ...

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Product Description 1.4 ATM Cell Processing Functions 1.4 ATM Cell Processing Functions Figure 1-3 received octet data from the line framers into ATM cells. During transmit, this block constructs ATM cells for the line transmitter circuits. The ATM cell ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 1.4.1 Cell Generation Functions The CN8223 ATM cell processing block provides flexible control for cell generation. Cell generation is the formatting of 48-octet payload segments into 53-octet ATM cells, and the generation of appropriate ...

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Product Description 1.5 FIFO Port/UTOPIA Interface 1.5 FIFO Port/UTOPIA Interface The CN8223 FIFO Port/UTOPIA interface is the data connection for the host system. modes for interfacing with ATM cells: four FIFO ports or one ATM Forum Level 1 Compliant ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 1.5.3 ATM Interface Each cell is sent to a buffer to allow for header processing before being output to the ATM interface. The buffer length is 10 octets for G.751 PLCP modes, and 6 ...

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Product Description 1.6 Line Interface Applications 1.6 Line Interface Applications With minimal glue logic, the CN8223 provides interfaces to STS-3c, STM-1, DS3, E3, TAXI, DS1 equipment. Multiple line rates can be supported with a single design if ...

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... Bt8222EPFE All Bt8222KPFD/EPFD functionality plus: RMRKR[1] was changed kHz output synchronized to the received PLCP frame. Bt8222EPFF All Bt8222EPFE functionality plus: Line Loopback (bit 9) in the CONFIG_3 register (0x02) is cleared upon assertion of RESET (pin 118). Receive STS/SDH pointer processing complies with standards. ...

Page 24

Product Description 1.8 CN8223 Applications 1.8 CN8223 Applications The CN8223 can be connected to several types of framers and PMDs. illustrates a general application where the CN8223 is connected to either a CAT 5 or Fiber Optic PMD. CN8223 ...

Page 25

CN8223 ATM Transmitter/Receiver with UTOPIA Interface Figure 1-8 Bt8510 External E1 Framer. the CN8223 using a Bt8370 External T1/E1 Framer. Figure 1-8. CN8223 Connected to Bt8510 Pin Cells ATM Layer Figure 1-9. CN8223 Connected to Bt8370 Pin Cells ATM Layer ...

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Product Description 1.8 CN8223 Applications Figure 1-10 TDK 78P7200 T3 LIU. Unused pins on the CN8223 must be tied as follows: unused RXIN_8:0 pins tie to ground, PECL inputs RXCKI_HS±, RXIN_HS±, and TXCKI_HS± tie Figure 1-10. ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 1.9 Logic Diagram The CN8223 is a single CMOS integrated circuit, packaged in a 160-pin Plastic Quad Flat Pack (PQFP). framer/PHY interface consists of 33 pins. The framing overhead interface consists of 22 pins. ...

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Product Description 1.9 Logic Diagram Figure 1-11. CN8223 Logic Diagram I 10 Receive Clock Input 11,12 Receive Clock In PECL I I 20,21 Receive Serial In PECL 15–19, 154,155 I 22,25 Receive Input 30 Transmit Clock Input I 23,24 ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 1.10 Pin Definitions Figure 1-12 Table 1-2 connected to ground and unused outputs should be left unconnected. However, if pins TXOVH_7 to TXOVH_0 or RXIN_8 to RXIN_0 are not used, they must be tied ...

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Product Description 1.10 Pin Definitions Table 1-2. Hardware Signal Definitions ( Pin Label Signal Name RXCKI Receive Clock Input RXCKI_HS– Receive Clock RXCKI_HS+ Input RXIN_HS– Receive Serial RXIN_HS+ Input RXIN[0] Receive Input RXIN[1] RXIN[2] RXIN[3] RXIN[4] RXIN[5] ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface Table 1-2. Hardware Signal Definitions ( Pin Label Signal Name TXOVH[0] Transmit Overhead TXOVH[1] Bus TXOVH[2] TXOVH[3] TXOVH[4] TXOVH[5] TXOVH[6] TXOVH[7] RXOVH[0] Receive Overhead RXOVH[1] Bus RXOVH[2] RXOVH[3] RXOVH[4] RXOVH[5] RXOVH[6] RXOVH[7] ...

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Product Description 1.10 Pin Definitions Table 1-2. Hardware Signal Definitions ( Pin Label Signal Name FDAT_IN[0] FIFO Data Bus FDAT_IN[1] FDAT_IN[2] FDAT_IN[3] FDAT_IN[4] FDAT_IN[5] FDAT_IN[6] FDAT_IN[7] FDAT_IN[8] FCTRL_IN[0] FIFO Control Input FCTRL_IN[1] FCTRL_IN[2] FCTRL_IN[3] FCTRL_IN[4] FCTRL_IN[5] FCTRL_IN[6] ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface Table 1-2. Hardware Signal Definitions ( Pin Label Signal Name SEL8BIT 8/16 Bit Mode Select PRCLK Processor Clock CS~ Chip Select AS~ Address Strobe W/R~ Write/Read Control OE~ Output Enable DL_INT FEAC/HDLC ...

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Product Description 1.10 Pin Definitions Table 1-2. Hardware Signal Definitions ( Pin Label Signal Name A[1] Address Bus A[2] A[3] A[4] A[5] A[6] A[7] 8KCKI 8 kHz Reference Clock Input ONESECI One-Second Clock Sync RCV_HLD Receiver Hold ...

Page 35

Functional Description This chapter describes the CN8223 architecture and functional blocks. and Figure 2-2 Figure 2-1. CN8223 Receiver Block Diagram Clock, Sync, Serial Data Serial Bipolar Data DS-3/G.751 Serial MUX E3 Framer NRZ Data Enable STS-1/ B3ZS/HDB3 STS-3c/ G.832 ...

Page 36

Functional Description 2.1 Microprocessor Interface 2.1 Microprocessor Interface All control and status functions are provided via a direct microprocessor interface. Address maps for the microprocessor are given in are two types of address spaces: • Read and write control ...

Page 37

CN8223 ATM Transmitter/Receiver with UTOPIA Interface 2.2 Line Framers This section describes the operation and control of the internal framers for DS3, E3 (both G.751 and G.832), E4 (G.832), STS-1, and STS-3c/STM-1 formatted serial streams. The transmit and receive serial ...

Page 38

Functional Description 2.2 Line Framers 2.2.1 Internally Framed Transmit Line Interface In internal framer mode, the transmitter provides positive and negative pulse indications and a transmit output clock to an external Line Interface Unit (LIU) (or output clock and ...

Page 39

CN8223 ATM Transmitter/Receiver with UTOPIA Interface 2.2.1.1 High-Speed For STS-3c, STM-1, or E4, the high-speed PECL interface is used. This mode is PECL Transmit Interface used in any case where an external LIU/decoder is used (such as E4 and STS-3c/STM-1 ...

Page 40

Functional Description 2.2 Line Framers 2.2.2 Internally Framed Receive Line Interface In internal framer mode, the receiver inputs are positive and negative pulse indications, and the receive clock (and NRZ serial data if internal B3ZS/HDB3 decoding is disabled) comes ...

Page 41

CN8223 ATM Transmitter/Receiver with UTOPIA Interface 2.2.2.1 High-Speed STS-3c, STM-1 and E4 use the high-speed PECL interface. This mode is used in PECL Receive Interface any case where an external LIU/decoder is used (such as E4 and STS-3c/STM-1 CMI decoding). ...

Page 42

Functional Description 2.2 Line Framers 2.2.3 Externally Framed Transmit Line Interface In external framer mode, the transmitter inputs are a clock and a synchronization signal that indicate the position of framing bits in the DS1, E1, DS3 ...

Page 43

CN8223 ATM Transmitter/Receiver with UTOPIA Interface Figure 2-8 2.048 MHz. TXSYI has a rising edge prior to the sampling of the first bit of time slot 0. This signal can be present every 2 ms. TXDATO is the output signal; ...

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Functional Description 2.2 Line Framers Figure 2-9 frequency of 44.736 MHz. TXSYI (active low) is sampled on falling clock transitions, and TXDATO changes on falling clock edges. TXSYI has a rising edge after the sampling of the overhead bit ...

Page 45

CN8223 ATM Transmitter/Receiver with UTOPIA Interface Figure 2-10 frequency of 34.368 MHz. TXSYI has a rising edge after the sampling of the last bit of the frame alignment signal. TXDATO is the output signal; it transitions in response to the ...

Page 46

Functional Description 2.2 Line Framers The input timings are all similar: RXDATI and RXSYI are sampled on the falling edge of the input clock; and the low-to-high transition of the sync signal occurs during the interval of the frame ...

Page 47

CN8223 ATM Transmitter/Receiver with UTOPIA Interface 2.3 Overhead Generation The CN8223 automatically receives and generates line overhead. For additional flexibility, line overhead can be monitored and inserted for STS-3c, STM-1, and G.832 E3/E4 modes. 2.3.1 Internal DS3 Mode The transmitter ...

Page 48

Functional Description 2.3 Overhead Generation 2.3.2 Internal G.832 E3/E4 Modes All framing overhead is generated automatically and the BIP octet is calculated and inserted in the EM position. The BIP field can be errored using the TXFEAC_ERRPAT register [0x03] ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 2.3.4 STS-1 and STS-3c/STM-1 Modes All framing overhead is generated automatically and all BIP overhead is calculated and inserted in the proper positions. BIP fields can be errored using the TXFEAC_ERRPAT register [0x03] and ...

Page 50

Functional Description 2.3 Overhead Generation Table 2-12. STS-1, STS-3c, and STM-1 Overhead Values ( Overhead Byte H4 This byte is no longer used by the CN8223. Its value is insignificant the number of octets between ...

Page 51

CN8223 ATM Transmitter/Receiver with UTOPIA Interface 2.3.5 Transmit Framing Overhead Interface An octet interface is available for external insertion of certain framing overhead in STS-1/STS-3c/STM-1 and G.832 E3/E4 framing modes. The interface consists of an output clock on TOVH_CLK, an ...

Page 52

Functional Description 2.3 Overhead Generation 2.3.6 Receive Framing Overhead Interface An octet interface is available for external observation of all framing overhead in STS-1/STS-3c/STM-1 and G.832 E3/E4 framing modes. The interface consists of two output clocks on ROVH_CLK[1,0], two ...

Page 53

CN8223 ATM Transmitter/Receiver with UTOPIA Interface 2.4 Status and Alarms The CN8223 automatically receives and generates alarms. 2.4.1 Status and Counter Interrupts The status interrupt pin STAT_INT can be programmed to provide an interrupt on any occurrence in the LINE_STATUS ...

Page 54

Functional Description 2.4 Status and Alarms 2.4.2 Alarm Signal Generation Three alarm signals can be generated by the transmitter in DS3 mode. These alarms are generated by setting Transmit Alarm Control [bits 6–4] of the CONFIG_2 register [0x01]. The ...

Page 55

CN8223 ATM Transmitter/Receiver with UTOPIA Interface 2.4.3 Alarm Detection The internal framers contain status indicators to obtain alarm information for link maintenance. repeated as Table 2-13. Status Indications for All Modes (Register 0x38) STS-1/STS-3c/ Bit Internal DS3 STM-1 15 Line ...

Page 56

Functional Description 2.5 Parallel Line Interface 2.5 Parallel Line Interface The CN8223 has a parallel line interface consisting of TXOUT[8:0] and RXOUT[8:0]. These octet ports allow interfacing of external framers or other devices that use parallel data. interface. Also, ...

Page 57

CN8223 ATM Transmitter/Receiver with UTOPIA Interface Timing information for TAXI mode is found in for the TAXI chipset and the CN8223 are listed in Table 2-14. Pin Connections between TAXI Chipset and CN8223 Receive Clock (CLK) Receive Data (DO 7-0) ...

Page 58

Functional Description 2.5 Parallel Line Interface Figure 2-14. Transmit Parallel Interface Timing TXCKI TXDAT[7:0] TXOD TXDELO 2-24 ATM Transmitter/Receiver with UTOPIA Interface Data Data Conexant CN8223 Data 100046C ...

Page 59

CN8223 ATM Transmitter/Receiver with UTOPIA Interface 2.5.3 Receive Parallel Interface Interface connections for the Receive Parallel Interface mode are listed in Table parallel mode, data octets are provided on RXDAT[7:0] with an octet clock ( MHz) on RXCKI. ...

Page 60

Functional Description 2.6 ATM Cell Processing 2.6 ATM Cell Processing The ATM cell processing block is located between the line framers and FIFO port blocks of the CN8223 (see the octet data and cell data portions of the chip. ...

Page 61

CN8223 ATM Transmitter/Receiver with UTOPIA Interface Two rate control registers are provided for control of the port sources to allow programmable rate shaping of cell transmission. The ratio of active to idle cells is programmable with 0.4 % granularity. The ...

Page 62

Functional Description 2.6 ATM Cell Processing Table 2-18. Overhead Field Locations Cell Header Header Error Control Segment Type Sequence Count Length Field Payload CRC Disable HEC [bit 9] and Disable Payload CRC [bit 10] in the CELL_GEN_x registers [0x04–0x07], ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 2.6.2 Cell Validation for Receive Cell validation refers to the checking of cells coming in from the PHY block for proper format. Modes that deliver 48-, 52- or 53-octet cells, or 57-octet PLCP slots ...

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Functional Description 2.6 ATM Cell Processing 2.6.2.1 HEC Alignment In 53-octet mode, either the internal framer or the parallel input provides octet alignment information to the HEC alignment state machine. Each octet position is then searched for correct HEC ...

Page 65

CN8223 ATM Transmitter/Receiver with UTOPIA Interface Table 2-19. Status Octet Definition Table 2-20. PT Header Field and User Data Bit If Disable Cell Receiver [bit 14] of CELL_VAL and Disable Port Reception— Port X [bits 7–4] of CONFIG_4 [0x29] are ...

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Functional Description 2.6 ATM Cell Processing . All errors disabled by the global disables in CELL_VAL are counted, and the first enabled error in the above sequence of checks is counted in the appropriate cell error counter. Disabled errors ...

Page 67

CN8223 ATM Transmitter/Receiver with UTOPIA Interface Counter overflow interrupts can be individually enabled counter is set to interrupt, it rolls over to zero, sets the interrupt, and continues counting errors after it reaches its maximum value ...

Page 68

Functional Description 2.6 ATM Cell Processing This capability can be used to verify far-end FEBE operation. BIP generation can be disabled via the Overhead Control bits. The fields of the G1 octet are under control of the All 0s ...

Page 69

CN8223 ATM Transmitter/Receiver with UTOPIA Interface 2.6.4 PLCP Cell Validation for Receive In 57-octet PLCP formats, the PHY receiver implements framing state machines for cell alignment as described in TR-TSV-000773. In 53-octet formats, the PHY receiver implements the HEC alignment ...

Page 70

Functional Description 2.6 ATM Cell Processing Each rising edge at the ONESECI input causes an indication in the One-Second Count bit. This indication can be used as a timing interrupt to coordinate status collection. If Enable One-second Latching of ...

Page 71

CN8223 ATM Transmitter/Receiver with UTOPIA Interface 2.7 FIFO Port/UTOPIA Interface The CN8223 has four bidirectional FIFO ports used to interface to the ATM layer outside the chip. These four ports share FDAT_IN and FDAT_OUT 8-bit ports. Each port has its ...

Page 72

Functional Description 2.7 FIFO Port/UTOPIA Interface Table 2-23. FIFO Interface Pin Connections ( FCTRL_OUT[7] FCTRL_OUT[8] FCTRL_OUT[9] FCTRL_OUT[10] FCTRL_OUT[11] FCTRL_OUT[12] FCTRL_OUT[13] FCTRL_OUT[14] FCTRL_OUT[15] FCTRL_OUT[16] NOTE(S): (1) FIFO read strobes are forced inactive (high) during hardware or software resets. ...

Page 73

CN8223 ATM Transmitter/Receiver with UTOPIA Interface Table 2-24. FIFO Transmit Pin Functional Descriptions CN8223 FIFO Pin Function Transmit Data FIFO Empty In the transmit direction, the Transmit Data FIFO Empty input inhibits the Transmit Data Read Strobe for a particular ...

Page 74

Functional Description 2.7 FIFO Port/UTOPIA Interface Table 2-25. FIFO Receive Pin Descriptions CN8223 FIFO Input Receive Data Write Strobe The receive data FIFO interface strobes data octets from FDAT_OUT[8:0] into an external FIFO device on each rising edge of ...

Page 75

CN8223 ATM Transmitter/Receiver with UTOPIA Interface If a higher priority port indicates that it has a cell ready during servicing of a lower priority port, service switches to the higher priority port after completion of the cell currently being formatted ...

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Functional Description 2.7 FIFO Port/UTOPIA Interface 2.7.4.1 Header The HDR_MSKx_12 and HDR_MSKx_34 registers further qualify the bitwise Screening values in the Header Value registers. There are four sets of these registers ( 3), one set ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface If Delete Idle Cells [bit 2] of CONFIG_4 [0x29] is set, then received cells matching the idle header and mask criteria are automatically screened from appearing on the output of all ports. This idle ...

Page 78

Functional Description 2.8 FEAC Channel and HDLC Data Link Programming 2.8 FEAC Channel and HDLC Data Link Programming This section discusses the use and programming requirements for the FEAC channel and HDLC data link. The FEAC channel is used ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 2.8.2 FEAC Channel Receiver The FEAC channel receiver is under control only of the received data stream. The receiver interrupt is under control of Enable Receive FEAC Interrupt [bit 8] in TXFEAC_ERRPAT. This interrupt ...

Page 80

Functional Description 2.8 FEAC Channel and HDLC Data Link Programming The transmitter implements an HDLC data link per ITU standard Q.921. The functions provided by the data link transmitter circuitry are transparency zero stuffing, Frame Check Sequence (FCS) generation, ...

Page 81

CN8223 ATM Transmitter/Receiver with UTOPIA Interface The 3-bit field TxBytes[2:0] is functionally split into two parts. The most significant bit (MSB) indicates to the transmitter circuitry which half of the buffer to read from next. The two LSBs indicate the ...

Page 82

Functional Description 2.8 FEAC Channel and HDLC Data Link Programming 2.8.3.4 Transmitter This example shows the sequence necessary to transmit a 10-byte hex message Control Example starting in the low half of the transmit buffer. With the transmitter in ...

Page 83

CN8223 ATM Transmitter/Receiver with UTOPIA Interface 2.8.4.1 Receiver The receiver implements an HDLC data link per ITU standard Q.921. The Operation functions provided by the data link receiver circuitry are transparency-zero removal, FCS checking, idle flag reception, and abort flag ...

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Functional Description 2.8 FEAC Channel and HDLC Data Link Programming Alternatively, the FCS data may be ignored, and the good or bad indication used directly important that software strategies allow for the fact that the LAPD receiver ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 2.8.5 Receiver Response Example The following example shows the sequence necessary to receive an 8-byte hex message that was stored starting in the low half of the receive buffer. In this example, the final ...

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Functional Description 2.8 FEAC Channel and HDLC Data Link Programming 2-52 ATM Transmitter/Receiver with UTOPIA Interface Conexant CN8223 100046C ...

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Registers 3.1 Registers Overview Table 3-1 displays an overview of the CN8223 registers. All registers are 16-bit, and the addresses are on 16-bit boundaries. There are seven address pins, A[7:1]. A[0] is always 0; therefore, it does not ...

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Registers 3.2 Control Register Overview 3.2 Control Register Overview Table 3-2 lists the 52 control registers of the CN8223. Control registers are realized as latches within the CN8223 and are programmed by a write operation from the microprocessor. No ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface Table 3-2. ATM Transmitter/Receiver Microprocessor Control Registers ( Address Name 0x16 HDR_VAL0_34 0x17 HDR_VAL1_12 0x18 HDR_VAL1_34 0x19 HDR_VAL2_12 0x1A HDR_VAL2_34 0x1B HDR_VAL3_12 0x1C HDR_VAL3_34 0x1D HDR_MSK0_12 0x1E HDR_MSK0_34 0x1F HDR_MSK1_12 0x20 HDR_MSK1_34 ...

Page 90

Registers 3.3 Configuration Control Registers 3.3 Configuration Control Registers 0x00—CONFIG_1 (Configuration Control Register 1) The CONFIG_1 register is located at address 0x00. This register sets chip parameters for both transmit and receive operations. The line interface type is set ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface Field Bit Name Size 7 1 Enable HEC Alignment 6 1 Enable Parallel Interface 5 1 External Framer 4 1 Disable B3ZS/HDB3 3 1 Unframed Input 2–0 3 PHY Type 100046C Description Enables cell ...

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Registers 3.3 Configuration Control Registers Table 3-3. Valid Combinations of CONFIG_1, Bits 0–7 Type of Line Input Signal DS1 DS1 (externally gapped 192 bits/frame (externally gapped TS0 and TS16) DS3, Internal Framer DS3, External Framer DS3, External ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 0x01—CONFIG_2 (Configuration Control Register 2) The CONFIG_2 register is located at address 0x01 and controls transmit formatting and alarm generation. Table 3-4 defines Alarm Controls for the Line Framing/PHY Formats. STS-1/STS-3c/STM-1. Table 3-6 defines ...

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Registers 3.3 Configuration Control Registers Table 3-4. Alarm Transmission Line Framing/PHY Format 53-Octet DS1, E1 Modes 57-Octet External (PHY types 0–3) 57-octet Internal DS3 Mode 57-octet Internal G.751 E3 Mode E3/E4 G.832 (PHY types 4–5) 53-octet Internal DS3 mode ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 0x02—CONFIG_3 (Configuration Control Register 3) The CONFIG_ 3 register is located at address 0x02 and controls miscellaneous functions. Field Bit Name Size 15–12 4 Accept/Reject Header–Port 3– Count Block Errors 10 1 ...

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Registers 3.3 Configuration Control Registers Field Bit Name Size 4 1 Check Input Parity 3 1 Disable Write Strobes on Invalid Cells 2 1 Enable DS1 PRS Generator 1 1 HEC Coverage 0 1 Enable HEC Coset 0x29—CONFIG_4 (Configuration ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 0x31—CONFIG_5 (Configuration Control Register 5) The CONFIG_5 register is located at address 0x31 and controls miscellaneous functions. Bits 3–0 are control bits which can be written and read. Bits 10, 9, and 8 are ...

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Registers 3.3 Configuration Control Registers 0x2B—UTOPIA_1 (Utopia Port Control Register 1) The UTOPIA_1 register is located at address 0x2B and controls operation of the UTOPIA interface. Operation of the UTOPIA interface is detailed in Field Bit Name Size 15–7 ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface Use the following steps to initialize the CN8223 for proper UTOPIA port operation 0x2C—UTOPIA_2 (Utopia Port Control Register 2) The UTOPIA_2 register is located at ...

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Registers 3.4 Transmit Control Registers 3.4 Transmit Control Registers 0x03—TXFEAC_ERRPAT (Transmit FEAC/Error Pattern Register) The TXFEAC_ERRPAT register is located at address 0x03. The eight MSBs control the FEAC channel used for DS3. Programming of the FEAC channel is discussed ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 0x60—DL_CTRL_STAT (HDLC Data Link Control and Status Register) The DL_CTRL_STAT register is located at address 0x60. The eight LSBs of this register are control bits and can be read or written. The eight MSBs ...

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Registers 3.4 Transmit Control Registers 0x04–0x07—CELL_GEN_x (Cell Generation Control Registers) The CELL_GEN_x registers are located at addresses 0x04–0x07. Each of the four FIFO ports has its own ATM Cell Generation Control Register ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 0x08—TX_RATE_23 (Transmit Rate Control Register) The TX_RATE_23 register is located at address 0x08. Each 8-bit field controls the maximum transmission rate for ports These fields are used to control the percentage ...

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Registers 3.4 Transmit Control Registers 0x2A—IDLE_PAY (Transmit Idle Cell Payload Register) The IDLE_PAY register is located at address 0x2A. This register sets the ATM idle cell payload contents. Field Bit Name Size 15–9 7 Reserved 8 1 Enable Idle ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 3.5 Receive Control Registers 0x14—CELL_VAL (Cell Validation Control Register) The CELL_VAL register is located at address 0x14. Validation checks performed by the validation process can be individually disabled with the “Disable” control bits. These ...

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Registers 3.5 Receive Control Registers Field Bit Name Size 5–4 2 Cell Output Mode-Port 2 3–2 2 Cell Output Mode-Port Cell Output Mode-Port 0 3-20 ATM Transmitter/Receiver with UTOPIA Interface Description Number of ATM cell ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 0x15–0x1C—HDR_VALx_12, HDR_VALx_34 (Receive Header Value Register) The Receive Header Value registers for port x (where x can are located at addresses 0x15–0x1C. The header values direct ATM cells to each ...

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Registers 3.5 Receive Control Registers 0x1D–0x24—HDR_MSKx_12, HDR_MSKx_34 (Receive Header Mask Register) The Receive Header Mask registers for port x (where x can are located at addresses 0x1D–0x24. These registers modify the ATM cell screen in ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 0x25, 0x26—RX_IDLE_12, RX_IDLE_34 (Receive Idle Header Registers) The Receive Idle Header Value registers are located at addresses 0x25 and 0x26. These registers define ATM idle cells for the cell receiver. Idle cells are counted ...

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Registers 3.6 Interrupt Enable Control Registers 3.6 Interrupt Enable Control Registers Four registers enable interrupts to appear on the STAT_INT interrupt output pin (pin 64). The EN_LINE_INT (0x2D), EN_EVENT_INT (0x2E), EN_OVFL_INT (0x2F), and EN_CELL_INT (0x30) enable interrupts based on ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 0x2E—EN_EVENT_INT (Enable Event Interrupts) The EN_EVENT_INT register is located at address 0x2E and enables interrupts for the EVENT_STATUS register (0x39). Setting a bit in EN_EVENT_INT enables each interrupt condition to appear on STAT_INT. Field ...

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Registers 3.6 Interrupt Enable Control Registers 0x2F—EN_OVFL_INT (Enable Overflow Interrupts) The EN_OVFL_INT register is located at address 0x2F and enables interrupts for the OVFL_STATUS register (0x3A). Setting a bit in EN_OVFL_INT enables each interrupt condition to appear on STAT_INT. ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 0x30—EN_CELL_INT (Enable Cell Interrupts) The EN_CELL_INT register (0x30) enables interrupts for the CELL_STATUS register (0x3B). Setting a bit in EN_CELL_INT enables each interrupt condition to appear on STAT_INT (pin 64). Field Bit Name Size ...

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Registers 3.7 Status Register Overview 3.7 Status Register Overview There are four status registers, as defined in registers will be cleared when read, or have separate clear functions. The status indications can interrupt the microprocessor if the corresponding bit ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 0x38—LINE_STATUS (Line Framer/PHY Interrupt Status Register) The LINE_STATUS register is located at address 0x38. Bit definitions for this register depend on the line interface mode selected. LINE_STATUS indicates alarms, errors, and framing states of ...

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Registers 3.7 Status Register Overview Table 3-12. STS-1,STS-3c, STM-1 LINE_STATUS Bit Definitions Bit Name 15 Line FEBE Error Set if any valid non-0 FEBE value (values 1–24) is detected in the M1 octet of the STS-1/STS-3c/STM-1 overhead. 14 One-Second ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface Table 3-13 provides definitions for the DS3 PLCP and Direct Mapping Mode LINE_STATUS bits. Table 3-13. DS3 PLCP and Direct Mapping Mode LINE_STATUS Bit Definitions Bit Name 15 0 Not used 14 One-Second Count ...

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Registers 3.7 Status Register Overview Table 3-14 lists definitions for E3 G.832 and E4 G.832 LINE_STATUS bits. Table 3-14. E3 G.832, E4 G.832 LINE_STATUS Bit Definitions Bit Name 15 0 Not used 14 One-Second Count Set if the one-second ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface Table 3-15 lists definitions for E3 G.751 LINE_STATUS bits. Table 3-15. E3 G.751 LINE_STATUS Bit Definitions Bit G.751 Not used 14 One-Second Count Set if the one-second timer input is detected. ...

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Registers 3.7 Status Register Overview Table 3-16 lists definitions for External Framer, 57-Octet Mode, LINE_STATUS bits. Table 3-16. External Framer, 57-Octet Mode, LINE_STATUS Bit Definitions Ext. Framer Bit (57 octet Not used 14 One Second Count Set ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface Table 3-17 lists status indications for all modes. Table 3-17. Status Indications for All Modes STS-1/STS-3 Bit Internal DS3 c/STM-1 15 Line FEBE 0 Error 14 One-Sec. One-Second Count Count 13 Signal Label Invalid ...

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Registers 3.7 Status Register Overview 0x39—EVENT_STATUS (Event Interrupt Status Register) The EVENT_STATUS register is located at address 0x39 and has receiver status conditions. Field Bit Name Size 15 1 Receiver Hold Input 14–13 2 Reserved 12 1 APS Event ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 0x3A—OVFL_STATUS (Counter Overflow Interrupt Status Register) The OVFL_STATUS register is located at address 0x3A and indicates when particular counters have overflowed. Error and Event Counters are described in Field Bit Name Size 15 1 ...

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Registers 3.7 Status Register Overview 0x3B—CELL_STATUS (Interrupt Status Register) The CELL_STATUS register is located at address 0x3B. Field Bit Name Size 15 1 Cell Sent Cntr Ovfl–Port 3 1 Cell Sent Cntr Ovfl–Port Cell Sent ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 3.8 Event/Error Counters The 24 counters to count line and interface events or errors are summarized in Tables 3-20 through Table 3-24. The first nine (addresses 0x40–0x48) provide counts of error events from the ...

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Registers 3.8 Event/Error Counters Table 3-19. Counted Events Ext. Framer Cntr Internal DS3 (57 octet) 1 Not Used 2 Not Used Frame Errors 3 Not Used Parity Errors 4 LOCD Events Path Parity Errors (Parallel interface) 5 Not Used ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface Table 3-20. Internal STS-1, STS-3c Event/Error Counters Address Counter Name 0x40 LINE_ PHY_CNTR_1 0x41 LINE_ PHY_CNTR_2 0x42 LINE_ PHY_CNTR_3 0x43 LINE_ PHY_CNTR_4 0x44 LINE_ PHY_CNTR_5 0x45 LINE_ PHY_CNTR_6 0x46 LINE_ PHY_CNTR_7 0x47 LINE_ PHY_CNTR_8 ...

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Registers 3.8 Event/Error Counters Table 3-21. Internal DS3 PLCP and Direct Mapping Modes Event/Error Counters Address Counter Name 0x40 LINE_ PHY_CNTR_1 Line Code Violation (LCV) in B3ZS/HDB3 decoder when enabled. For B3ZS this counts both bipolar rule violations and ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface Table 3-22. Internal G.832 E3/E4 Event/Error Counters Address Counter Name 0x40 LINE_ PHY_CNTR_1 Line code violation in B3ZS/HDB3 decoder when enabled. For B3ZS this counts both bipolar rule violations and occurrences of three or ...

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Registers 3.8 Event/Error Counters Table 3-23. Internal G.751 E3 Event/Error Counters Address Counter Name 0x40 LINE_ PHY_CNTR_1 0x41 LINE_ PHY_CNTR_2 0x42 LINE_ PHY_CNTR_3 0x43 LINE_ PHY_CNTR_4 0x44 LINE_ PHY_CNTR_5 0x45 LINE_ PHY_CNTR_6 0x46 LINE_ PHY_CNTR_7 0x47 LINE_ PHY_CNTR_8 0x48 ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface Table 3-24. External Framer, 57-Octet Mode Event/Error Counters Address Counter Name 0x40 LINE_ PHY_CNTR_1 0x41 LINE_ PHY_CNTR_2 0x42 LINE_ PHY_CNTR_3 0x43 LINE_ PHY_CNTR_4 0x44 LINE_ PHY_CNTR_5 0x45 LINE_ PHY_CNTR_6 0x46 LINE_ PHY_CNTR_7 0x47 LINE_ ...

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Registers 3.8 Event/Error Counters Figure 3-2. Register Summary, Cheat Sheet 1 3-46 ATM Transmitter/Receiver with UTOPIA Interface Conexant CN8223 100046C ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface Figure 3-3. Register Summary, Cheat Sheet 2 100046C Conexant 3.0 Registers 3.8 Event/Error Counters 3-47 ...

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Registers 3.8 Event/Error Counters 3-48 ATM Transmitter/Receiver with UTOPIA Interface Conexant CN8223 100046C ...

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Electrical and Mechanical Specifications This chapter discusses the electrical specifications of the CN8223, such as power requirements, temperature ranges, DC characteristics and timing. A mechanical drawing is included. 4.1 Power Requirements and Temperature Range The CN8223 meets all specifications ...

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Electrical and Mechanical Specifications 4.2 DC Characteristics 4.2 DC Characteristics All input and bidirectional pins have input thresholds compatible with CMOS drive levels except those labeled as xxxHS±. Leakage current for each pin is less than 10 µA in ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface Table 4-1 Table 4-1. DC Characteristics Symbol Parameter VT Switching threshold VT+ Schmitt Trigger, positive-going threshold VT– Schmitt Trigger, negative-going threshold Schmitt Trigger Input Hysteresis Voltage IIN Inputs Inputs with pulldown resistors (5 V) ...

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Electrical and Mechanical Specifications 4.3 Timing 4.3 Timing This section includes timing diagrams and descriptions for the CN8223. 4.3.1 Microprocessor Interface Timing Table 4-2 the microprocessor interface. All times are in nanoseconds. Table 4-2. Microprocessor Interface Timing Name t ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface Figure 4-1. Local Processor Interface Timing PRCLK Set Min (t and t ) aspr cspr W/R ~ VALID A[7:1] Set Min (t and t ...

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Electrical and Mechanical Specifications 4.3 Timing 4.3.2 Line Interface Timing Tables 4-3 requirements and characteristics of the line interfaces and parallel data and overhead ports. All times are in nanoseconds. Example LIU circuits are provided in CN8223 EVM schematics. ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface Figure 4-2. Line Interface Timing—DS1, E1, DS3, E3 External Framers TXCKI,TXCKIHS TXSYI TXDATO (DS1/E1) TXDATO (DS3/E3) RXCKI,RXCKIHS RXSYI RXDATI Table 4-4. Line Interface Timing—Internal Framers Name Interval t txcki 1–6 Transmit Clock Period t ...

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Electrical and Mechanical Specifications 4.3 Timing Figure 4-3. Line Interface Timing–Internal Framers TXCKI,TXCKIHS TCLKO TXDATO TXPOS, TXNEG RXCKI,RXCKIHS RXDATI RXPOS, RXNEG Table 4-5. Parallel Interface Timing Name Interval t txcki 1–4 Transmit Clock Period t txh 4–5 Transmit Clock ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface Figure 4-4. Parallel Interface Timing 1 TXCKI TXOD TXDAT[7:0] TXDELO RXCKI RXOD RXDAT[7:0] Table 4-6. Overhead Port Interface Timing Name Interval t ptx, t prx — Transmit or Receive Clock Input Period t tckh ...

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Electrical and Mechanical Specifications 4.3 Timing Figure 4-5. Overhead Port Interface Timing 2 4 TOVHCLK 1 TMRKR 3 Valid TXOVH[7:0] ROVHCLK[1] RMRKR[1] RXOVH[7:0] RXOVHCLK[0] RMRKR[0] 4-10 ATM Transmitter/Receiver with UTOPIA Interface Conexant CN8223 ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 4.3.3 FIFO Interface Timing Table 4-7 the FIFO port interface. All times are in nanoseconds. Table 4-7. FIFO Port Interface Timing Name Interval t ptx, t prx — Transmit or Receive Clock Input Period ...

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Electrical and Mechanical Specifications 4.3 Timing Figure 4-6. FIFO Port Interface Timing WRITE STROBE RX SYNC MARKER RX INVALID RX DATA OUT 3 FULL ~ INPUT WRT ERROR ~ OUTPUT READ STROBE TX ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 4.3.4 UTOPIA Interface Timing Table 4-8 the UTOPIA interface. All times are in nanoseconds. Table 4-8. UTOPIA Interface Timing Name Interval t 1–4 Transmit Clock Input Period T1 t 1–3 Transmit Clock High Pulse ...

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Electrical and Mechanical Specifications 4.3 Timing Figure 4-7. UTOPIA Interface Timing TxClk TxData TxPrty TxSOC TxFull ~ TxClav TxEnb ~ 9 11 RxClk RxData RxPrty RxSOC 10 RxEmpty ~ RxClav RxENB* 4-14 ATM Transmitter/Receiver with UTOPIA Interface 1 3 ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 4.3.5 TAXI Interface Timing Table 4-9 the TAXI interface. All times are in nanoseconds. Table 4-9. TAXI Interface Timing Name Interval t 1–5 Transmit Clock Input Period ptx t 1–3 Transmit Clock High Pulse ...

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Electrical and Mechanical Specifications 4.3 Timing Figure 4-8. TAXI Port Interface Timing TXCKI (CLK) TXCLKO (STRB) TXOUT[8] (CI 1) TXOUT[7:0] D[7:0] RXCKI (CLK) RCVHLD (CSTRB) TXIN (CO 1) RXIN[7:0] DO [7:0] RXIN[8] (VLTN) 4-16 ATM Transmitter/Receiver with UTOPIA Interface ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface 4.4 Mechanical Drawing The CN8223 is a 160-pin Plastic Quad Flat Pack (PQFP) as illustrated in Figure Figure 4-9. CN8223 160-Pin Plastic Quad Flat Pack TOP VIEW ALL DIMENSIONS ...

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Electrical and Mechanical Specifications 4.4 Mechanical Drawing 4-18 ATM Transmitter/Receiver with UTOPIA Interface Conexant CN8223 100046C ...

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A Appendix A: Transmit FIFO Port Rates This appendix describes the arbitration mechanism used to control and prioritize the Transmit FIFO port rate. The CN8223 has two options for its ATM layer interface: UTOPIA or FIFO mode. UTOPIA mode is ...

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Appendix A: Transmit FIFO Port Rates A.2 Port Priority A.2 Port Priority The user can define a priority for each port. This priority can range from with 0 being the highest priority. A higher priority port will ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface Table A-1. Cell Thresholds ( Slot Port 0 Port 1 Port 128 5 5 130 6 6 ...

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Appendix A: Transmit FIFO Port Rates A.3 Summary Table A-1. Cell Thresholds ( Slot Port 0 Port 1 Port 160 69 21 162 70 22 164 71 23 166 72 144 40 73 145 42 ...

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CN8223 ATM Transmitter/Receiver with UTOPIA Interface Table A-1. Cell Thresholds ( Slot Port 0 Port 1 Port 2 136 160 9 137 161 11 138 162 13 139 163 15 140 164 137 141 165 139 142 166 ...

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Appendix A: Transmit FIFO Port Rates A.3 Summary Table A-1. Cell Thresholds ( Slot Port 0 Port 1 Port 2 204 180 169 205 181 171 206 182 173 207 183 175 208 56 97 209 57 99 ...

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B Appendix B: Acronym List AAL AIS APS ATM BIP-8 BOM CMOS COM Coset CPE CRC EOM FAS FCS FEAC FEBE FERF FIFO HDLC HEC ISR LAPD LCV LIU LOC LOCD LOF LOS LSB MSB NNI NRZ OOF PECL PHY ...

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Appendix B: Acronym List POI PQFP RDI SDH SMDS SONET SPE SSM STS TAXI UNI UTOPIA VCI VPI B-2 ATM Transmitter/Receiver with UTOPIA Interface Path Overhead Identifier Plastic Quad Flat Pack Remote Defect Indication Synchronous Digital Hierarchy Switched Multimegabit Data ...

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... Further Information: literature@conexant.com 1-800-854-8099 (North America) 33-14-906-3980 (International) Web Site www.conexant.com World Headquarters Conexant Systems, Inc. 4311 Jamboree Road, P.O. Box C Newport Beach, CA 92658-8902 Phone: (949) 483-4600 Fax: (949) 483-6375 U.S. Florida/South America Phone: (727) 799-8406 Fax: (727) 799-8306 U.S. Los Angeles ...

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