UPD4701AC

Manufacturer Part NumberUPD4701AC
DescriptionMOS INTEGRATED CIRCUIT
ManufacturerNEC
UPD4701AC datasheet
 

Specifications of UPD4701AC

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INCREMENTAL ENCODER COUNTER
DESCRIPTION
The PD4701A is a counter for an X, Y 2-axis incremental encoder. When a two-phase encoder signal is input
for the X and Y axes, direction discrimination and computation is performed, and count data is output in 8-bit parallel
form. In addition, a 3-contact-point input buffer is incorporated, which is useful for applications which use a pointing
device such as a mouse or track-ball. The CPU checks the switch input flag or count flag and reads the 12-bit count
data in two operations, one for the lower byte and one for the upper byte. The key input flag is output together with
the count data in the upper byte.
FEATURES
• X, Y 2-axis incremental encoder counter
• Counter input (Schmitt-triggered input)
X axis: X
, X
2-phase signal
A
B
Y axis: Y
, Y
2-phase signal
A
B
• Counters: 12-bit binary up/down counters (2 sets, X & Y)
Reset value: 000H
• Count data output: 8-bit parallel latch output
• On-chip 3-contact-point key input buffer circuit
• CMOS
• Single +5 V power supply
PIN NAMES
X
, Y
: A-phase inputs
A
A
X
, Y
: B-phase inputs
B
B
RIGHT
LEFT
Key inputs
MIDDLE
CS
: Chip Select
X/Y
: X/Y Counter Select
U/L
: Upper/Lower Byte Select
D
: Data outputs
0 to 7
CF
: Count flag
RESET X Counter
SF
: Count flag
RESET Y
Document No. IC-3303 (1st edition)
(O. D. No. IC-6947A)
Date Published March 1997 P
Printed in Japan
DATA SHEET
MOS INTEGRATED CIRCUIT
4-multiplication count method used
2 (including key input flag)
PIN CONFIGURATION (Top View)
X
A
X
B
RESET X
Y
A
Y
B
RESET Y
RIGHT
LEFT
MIDDLE
reset inputs
SF
CF
V
SS
PD4701A
1
24
V
DD
2
23
D
7
3
22
D
6
4
21
D
5
5
20
D
4
6
19
D
3
7
18
D
2
8
17
D
1
9
16
D
0
10
15
CS
11
14
X/Y
12
13
U/L
©
1993

UPD4701AC Summary of contents