MC9S12Q128VFU16 Motorola, MC9S12Q128VFU16 Datasheet
MC9S12Q128VFU16
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MC9S12Q128VFU16 Summary of contents
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MC9S12Q128 Reference Manual Covers MC9S12Q Family HCS12 Microcontrollers Rev 1.09 MC9S12Q128 12/2007 freescale.com ...
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To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family Chapter 2 Port Integration Module (PIM9C32 ...
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MC9S12Q128 Rev 1.09 Freescale Semiconductor ...
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MC9S12Q Device Overview (MC9S12Q128-Family) 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Interrupt (INTV1) Block Description 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Setting up and starting an A/D conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PWM1 — Pulse Width Modulator Channel 1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 12.2.4 ...
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MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Flash Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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A.4.2 Oscillator ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.1 Introduction The MC9S12Q128-Family is a 48/52/80 pin Flash-based MCU family, which delivers the power and flexibility of the 16 Bit core to a whole new range of cost and space sensitive, general purpose ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) • Memory options: — 32Kbyte ROM or Flash EEPROM (erasable in 512-byte sectors) 64K, 96K, or 128Kbyte ROM or Flash EEPROM (erasable in 1024-byte sectors) — 1K, 2K Byte RAM • ...
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Bus Speed for single chip — 16MHz equivalent to 8MHz Bus Speed in expanded bus modes — Option of 32 MHz equivalent to 16MHz Bus Speed • Internal 2.5V regulator: — Supports an input voltage ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.1.3 Block Diagram Figure 1-1. MC9S12Q128-Family Block Diagram VSSR VDDR VDDX VSSX Voltage Regulator 32K, 64K, 96K, 128K Byte Flash/ROM VDD2 VSS2 VDD1 1K, 2K, 3K, 4K Byte RAM VSS1 Single-wire Background BKGD Debug12 ...
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Memory Map and Registers 1.2.1 Device Memory Map Table 1-1 shows the device register map after reset. memory map. Address 0x0000–0x0017 0x0018 0x0019 0x001A–0x001B 0x001C–0x001F 0x0020–0x002F 0x0030–0x0033 0x0034–0x003F 0x0040–0x006F 0x0070–0x007F 0x0080–0x009F 0x00A0–0x00C7 Reserved 0x00C8–0x00CF Serial communications interface (SCI) 0x00D0–0x00D7 ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) $0000 $0400 $3000 $4000 $8000 EXT $C000 $FF00 VECTORS VECTORS $FFFF NORMAL EXPANDED SINGLE CHIP The figure shows a useful map, which is not the map out of reset. After reset the map is: ...
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VECTORS $FFFF NORMAL SINGLE CHIP The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0400 - $0FFF: 3K ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) $0000 $0400 $3800 $4000 $8000 $C000 $FF00 VECTORS $FFFF NORMAL SINGLE CHIP The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: ...
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VECTORS $FFFF NORMAL SINGLE CHIP The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0C00 - $0FFF: 1K ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.2.2 Detailed Register Map The detailed register map of the MC9S12Q128-Family is listed in address order below. 0x0000–0x000F MEBI Map (HCS12 Multiplexed External Bus Interface) Address Name Read: 0x0000 PORTA Write: ...
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MMC Map (HCS12 Module Mapping Control) Address Name Read: 0x0010 INITRM Write: Read: 0x0011 INITRG Write: Read: 0x0012 INITEE Write: Read: 0x0013 MISC Write: Read: 0x0014 Reserved Write: 0x0015–0x0016 INT Map (HCS12 Interrupt) ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x001A–0x001B Miscellaneous Peripherals (Device User Guide) Address Name Read: 0x001A PARTIDH Write: Read: 0x001B PARTIDL Write: 0x001C–0x001D MMC Map (HCS12 Module Mapping Control, Device User Guide) Address Name Read: reg_sw0 0x001C ...
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DBG (Including BKP) Map (HCS12 Debug) (continued) Address Name Read: 0x0026 DBGCCH Write: Read: 0x0027 DBGCCL Write: DBGC2 Read: 0x0028 BKABEN BKPCT0 Write: DBGC3 Read: 0x0029 BKAMBH BKAMBL BKBMBH BKBMBL BKPCT1 Write: DBGCAX Read: 0x002A BKP0X ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x0034–0x003F CRG (Clock and Reset Generator) Address Name Read: 0x0034 SYNR Write: Read: 0x0035 REFDV Write: Read: CTFLG 0x0036 TEST ONLY Write: Read: 0x0037 CRGFLG Write: Read: 0x0038 CRGINT Write: Read: 0x0039 CLKSEL PLLSEL ...
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TIM Address Name Read: TTOV 0x0047 Write: Read: TCTL1 0x0048 Write: Read: TCTL2 0x0049 Write: Read: TCTL3 0x004A Write: Read: TCTL4 0x004B Write: Read: TIE 0x004C Write: Read: TSCR2 0x004D Write: Read: TFLG1 0x004E Write: Read: TFLG2 0x004F Write: ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x0040-0x006F TIM Address Name Read: TC6 (hi) 0x005C Write: Read: TC6 (lo) 0x005D Write: Read: TC7 (hi) 0x005E Write: Read: TC7 (lo) 0x005F Write: Read: PACTL 0x0060 Write: Read: PAFLG 0x0061 Write: Read: PACNT ...
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Reserved Address Name Read: 0x0070– Reserved 0x007F Write: 0x0080–0x009F ATD (Analog-to-Digital Converter 10 Bit 8 Channel) Address Name Read: 0x0080 ATDCTL0 Write: Read: 0x0081 ATDCTL1 Write: Read: 0x0082 ATDCTL2 Write: Read: 0x0083 ATDCTL3 Write: Read: 0x0084 ATDCTL4 Write: Read: ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x0080–0x009F ATD (Analog-to-Digital Converter 10 Bit 8 Channel) (continued) Address Name Read: 0x0093 ATDDR1L Write: Read: 0x0094 ATDDR2H Write: Read: 0x0095 ATDDR2L Write: Read: 0x0096 ATDDR3H Write: Read: 0x0097 ATDDR3L Write: Read: 0x0098 ATDDR4H ...
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SCI (Asynchronous Serial Interface) (continued) Address Name Read: 0x00CC SCISR1 Write: Read: 0x00CD SCISR2 Write: Read: 0x00CE SCIDRH Write: Read: 0x00CF SCIDRL Write: 0x00D0–0x00D7 Reserved Address Name Read: 0x00D0– Reserved 0x00D7 Write: 0x00D8–0x00DF SPI (Serial Peripheral Interface) Address Name ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x00E0-0x00FF PWM Address Name Read: PWME 0x00E0 Write: Read: PWMPOL 0x00E1 Write: Read: 0x00E2 PWMCLK Write: Read: PWMPRCLK 0x00E3 Write: Read: PWMCAE 0x00E4 Write: Read: PWMCTL 0x00E5 Write: Read: PWMTST 0x00E6 Test Only Write: ...
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PWM Address Name Read: PWMPER3 0x00E5 Write: Read: Reserved 0x00E6 Write: Read: Reserved 0x00E7 Write: Read: PWMDTY0 0x00E8 Write: Read: PWMDTY1 0x00E9 Write: Read: PWMDTY2 0x00EA Write: Read: PWMDTY3 0x00EB Write: Read: Reserved 0x00EC Write: Read: Reserved 0x00ED Write: ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x0100–0x010F Flash Control Register (continued) Address Name Read: Reserved for 0x0108 Factory Test Write: Read: Reserved for 0x0109 Factory Test Write: Read: Reserved for 0x010A Factory Test Write: Read: Reserved for 0x010B Factory Test ...
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CAN (Scalable Controller Area Network — MSCAN) (continued) Address Name Read: 0x0148 CANTARQ Write: Read: 0x0149 CANTAAK Write: Read: 0x014A CANTBSEL Write: Read: 0x014B CANIDAC Write: Read: 0x014C Reserved Write: Read: 0x014D Reserved Write: Read: RXERR7 RXERR6 RXERR5 RXERR4 ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) Table 1-2. Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued) Address Name Read: 0xXXX4– CANxRDSR0– 0xXXXB CANxRDSR7 Write: Read: 0xXXXC CANRxDLR Write: Read: 0xXXXD Reserved Write: Read: 0xXXXE CANxRTSRH Write: Read: 0xXXXF CANxRTSRL ...
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PIM (Port Interface Module) (Sheet Address Name Read: 0x0240 PTT Write: Read: 0x0241 PTIT Write: Read: 0x0242 DDRT Write: Read: 0x0243 RDRT Write: Read: 0x0244 PERT Write: Read: 0x0245 PPST Write: Read: 0x0246 Reserved Write: Read: ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 0x0240–0x027F PIM (Port Interface Module) (Sheet Address Name Read: 0x0256 WOMM Write: Read: 0x0257 Reserved Write: Read: 0x0258 PTP Write: Read: 0x0259 PTIP Write: Read: 0x025A DDRP DDRP7 Write: Read: 0x025B ...
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PIM (Port Interface Module) (Sheet Address Name Read: 0x026D PPSJ Write: Read: 0x026E PIEJ Write: Read: 0x026F PIFJ Write: Read: 0x0270 PTAD Write: Read: PTIAD7 0x0271 PTIAD Write: Read: 0x0272 DDRAD DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.2.3 Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and ox001B after reset). The read-only value is a unique part ID for each revision of ...
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Signal Description 1.3.1 Device Pinouts PW3/KWP3/PP3 1 PW2/KWP2/PP2 2 PW1/KWP1/PP1 3 PW0/KWP0/PP0 4 PW0/PT0 5 PW1/PT1 6 PW2/IOC2/PT2 7 PW3/IOC3/PT3 8 VDD1 9 VSS1 10 IOC4/PT4 11 IOC5/PT5 12 IOC6/PT6 13 IOC7/PT7 14 MODC/TAGHI/BKGD 15 ADDR0/DATA0/PB0 16 ADDR1/DATA1/PB1 17 ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) PW3/KWP3/PP3 1 PW0/PT0 2 PW1/PT1 3 PW2/IOC2/PT2 4 PW3/IOC3/PT3 5 VDD1 6 VSS1 7 IOC4/PT4 8 9 IOC5/PT5 10 IOC6/PT6 11 IOC7/PT7 12 MODC/BKGD 13 PB4 * Signals shown in Bold italic are not ...
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PW0/PT0 1 PW1/PT1 2 PW2/IOC2/PT2 3 PW3/IOC3/PT3 4 VDD1 5 VSS1 6 7 IOC4/PT4 8 IOC5/PT5 9 IOC6/PT6 10 IOC7/PT7 11 MODC/BKGD 12 PB4 Figure 1-8. Pin Assignments in 48-Pin LQFP Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 36 ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.3.2 Signal Properties Summary Pin Name Pin Name Pin Name Function 1 Function 2 Function 3 EXTAL — — XTAL — — RESET — — XFC — — TEST V — PP BKGD MODC ...
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Pin Name Pin Name Pin Name Function 1 Function 2 Function 3 PP[2:0] KWP[2:0] PW[2:0] PJ[7:6] KWJ[7:6] — PM5 SCK — PM4 MOSI — PM3 SS — PM2 MISO — PM1 TXCAN — PM0 RXCAN — PS[3:2] — — PS1 ...
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... XFC — PLL Loop Filter Pin Dedicated pin used to create the PLL loop filter. See CRG BUG for more detailed information.PLL loop filter. Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided. ...
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PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins PA7–PA0 are general purpose input or output pins,. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. PA[7:1] pins are ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) Figure 1-12. External Clock Connections (PE7 = 0) 1.3.4.9 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 PE6 is a general purpose input or output pin used as a ...
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PE2 / R/W — Port E I/O Pin [2] / Read/Write In all modes this pin can be used as a general-purpose I/O and is an input with an active pull-up out of reset. If the read/write function is ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the state of this pin is latched to the ROMON bit. • PP6 = 1 in emulation modes equates ...
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PS[3:2] — Port S I/O Pins [3:2] PS3 and PS2 are general purpose input or output pins. These pins are not available in the 48- / 52-pin package versions. 1.3.4.28 PS1 / TXD — Port S I/O Pin 1 ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.3.5 — Power Supply Pins for ATD and VREG DDA SSA are the power supply and ground input pins for the voltage regulator reference and the analog DDA ...
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System Clock Description The clock and reset generator provides the internal clock signals for the core and all peripheral modules. Figure 1-13 shows the clock connections from the CRG to all modules. Consult the CRG Block User Guide for ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) BKGD = PE6 = PE5 = PP6 = MODC MODB MODA ROMCTL ...
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The security byte resides in a portion of the Flash array. Check the Flash Block User Guide for more details on the security configuration. 1.5.2.2 Operation of the Secured Microcontroller 1.5.2.2.1 Normal Single Chip Mode This will be the most ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.5.3.3 Wait This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute instructions. The internal CPU signals (address and data bus) will be fully static. All ...
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Table 1-9. Interrupt Vector Locations (continued) Vector Address Interrupt Source 0xFFDA, 0xFFDB Pulse accumulator input edge 0xFFD8, 0xFFD9 0xFFD6, 0xFFD7 0xFFD4, 0xFFD5 0xFFD2, 0xFFD3 0xFFD0, 0xFFD1 0xFFCE, 0xFFCF 0xFFCC, 0xFFCD 0xFFCA, 0xFFCB 0xFFC8, 0xFFC9 0xFFC6, 0xFFC7 0xFFC4, 0xFFC5 CRG self ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.6.2 Resets Resets are a subset of the interrupts featured in system reset are summarized in changed to known start-up states. Refer to the respective module Block User Guides for register reset states. 1.6.2.1 ...
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Table 1-11. Device Specific Flash PAGE Mapping Device PAGE 3E $00,$02,$04,$06,$08,$0A,$0C,$0E,$10,$12......$2C,$2E,$30,$32,$34,$36,$38,$3A,$3C,$3E MC9S12Q32 3F $01,$03,$05,$07,$09,$0B,$0D,$0F,$11,$13.....$2D,$2F,$31,$33,$35,$37,$39,$3B,$3D,$ MC9S12Q64 MC9S12Q96 MC9S12Q128 1.7.2 BDM Alternate Clock The ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 1.7.4 VREGEN The VREGEN input mentioned in the VREG section is device internal, connected internally to V 1.7 DD1 DD2 SS1 In the 80-pin QFP package versions, both internal ...
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Recommended Printed Circuit Board Layout The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed: • Every supply pair must be ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) Figure 1-14. Recommended PCB Layout (48 LQFP) Colpitts Oscillator 66 MC9S12Q128 Rev 1.09 Freescale Semiconductor ...
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Figure 1-15. Recommended PCB Layout (52 LQFP) Colpitts Oscillator Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) MC9S12Q128 Rev 1.09 67 ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) Figure 1-16. Recommended PCB Layout (80 QFP) Colpitts Oscillator 68 MC9S12Q128 Rev 1.09 Freescale Semiconductor ...
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Figure 1-17. Recommended PCB Layout for 48 LQFP Pierce Oscillator Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) MC9S12Q128 Rev 1.09 69 ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) Figure 1-18. Recommended PCB Layout for 52 LQFP Pierce Oscillator 70 MC9S12Q128 Rev 1.09 Freescale Semiconductor ...
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Figure 1-19. Recommended PCB Layout for 80QFP Pierce Oscillator Freescale Semiconductor Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) MC9S12Q128 Rev 1.09 71 ...
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Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family) 72 MC9S12Q128 Rev 1.09 Freescale Semiconductor ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.1 Introduction The Port Integration Module establishes the interface between the peripheral modules and the I/O pins for all ports. This chapter covers: • Port A, B, and E related to the ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.1.2 Block Diagram Figure 2 block diagram of the PIM. PJ6 PJ7 PAD0 AN0 AN1 PAD1 AN2 PAD2 AN3 PAD3 PAD4 AN4 PAD5 AN5 AN6 PAD6 AN7 PAD7 PB0 ADDR0/DATA0 ...
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Signal Description This section lists and describes the signals that do connect off-chip. Table 2-1 shows all pins and their functions that are controlled by the PIM module. If there is more than one function associated to a pin, ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description Table 2-1. Pin Functions and Priorities (continued) Port Pin Name Pin Function NOACC/ PE7 XCLKS/ GPIO IPIPE1/ PE6 MODB/ GPIO IPIPE0/ PE5 MODA/ GPIO Port E PE4 ECLK/GPIO LSTRB/ PE3 TAGLO/ GPIO ...
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Address Name Bit 7 R 0x0006 Reserved W R 0x0007 MODRR W R 0x0008 PTS W SCI — R 0x0009 PTIS W R 0x000A DDRS W R 0x000B RDRS W R 0x000C PERS W R 0x000D PPSS W R 0x000E ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description Address Name Bit 7 R 0x001A DDRP DDRP7 W R 0x001B RDRP RDRP7 W R 0x001C PERP PERP7 W R 0x001D PPSP PPSP7 W R 0x001E PIEP PIEP7 W R 0x001F PIFP ...
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Register Descriptions Table 2-2 summarizes the effect on the various configuration bits — data direction (DDR), input/output level (I/O), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the ports. The configuration bit PS ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.1 Port T Registers 2.3.2.1.1 Port T I/O Register (PTT) Module Base + 0x0000 PTT7 PTT6 W TIM IOC7 IOC6 PWM Reset Unimplemented or Reserved Read: ...
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Port T Input Register (PTIT) Module Base + 0x0001 PTIT7 PTIT6 W Reset — — = Unimplemented or Reserved Read: Anytime. Write: Never, writes to this register have no effect. Field 7–0 Port T Input Register ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.1.4 Port T Reduced Drive Register (RDRT) Module Base + 0x0003 RDRT7 RDRT6 W Reset 0 0 Figure 2-6. Port T Reduced Drive Register (RDRT) Read: Anytime. Write: Anytime. ...
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Port T Polarity Select Register (PTTST) Module Base + 0x0005 PPST7 PPST6 W Reset 0 0 Figure 2-8. Port T Polarity Select Register (PPST) Read: Anytime. Write: Anytime. Field 7–0 Pull Select Port T — This ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.2 Port S Registers 2.3.2.2.1 Port S I/O Register (PTS) Module Base + 0x0008 SCI — — Reset Unimplemented or Reserved Read: Anytime. ...
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Port S Data Direction Register (DDRS) Module Base + 0x000A Reset Unimplemented or Reserved Figure 2-12. Port S Data Direction Register (DDRS) Read: Anytime. Write: Anytime. Field 3–0 Direction Register ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.2.4 Port S Reduced Drive Register (RDRS) Module Base + 0x000B Reset Unimplemented or Reserved Figure 2-13. Port S Reduced Drive Register (RDRS) ...
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Port S Polarity Select Register (PPSS) Module Base + 0x000D Reset Unimplemented or Reserved Figure 2-15. Port S Polarity Select Register (PPSS) Read: Anytime. Write: Anytime. Field 3–0 Pull Select ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.3 Port M Registers 2.3.2.3.1 Port M I/O Register (PTM) Module Base + 0x0010 MSCAN/ — — SPI Reset Unimplemented or Reserved Read: ...
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Port M Data Direction Register (DDRM) Module Base + 0x0012 Reset — — = Unimplemented or Reserved Figure 2-19. Port M Data Direction Register (DDRM) Read: Anytime. Write: Anytime. Field 5–0 Data Direction ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.3.4 Port M Reduced Drive Register (RDRM) Module Base + 0x0013 Reset Unimplemented or Reserved Figure 2-20. Port M Reduced Drive Register (RDRM) ...
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Port M Polarity Select Register (PPSM) Module Base + 0x0015 Reset Unimplemented or Reserved Figure 2-22. Port M Polarity Select Register (PPSM) Read: Anytime. Write: Anytime. Field 5–0 Polarity Select ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.4 Port P Registers 2.3.2.4.1 Port P I/O Register (PTP) Module Base + 0x0018 PTP7 PTP6 W PWM — — Reset 0 0 Read: Anytime. Write: Anytime. If the ...
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Port P Data Direction Register (DDRP) Module Base + 0x001A DDRP7 DDRP6 W Reset 0 0 Figure 2-26. Port P Data Direction Register (DDRP) Read: Anytime. Write: Anytime. Field 7–0 Data Direction Port P — This ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.4.5 Port P Pull Device Enable Register (PERP) Module Base + 0x001C PERP7 PERP6 W Reset 0 0 Figure 2-28. Port P Pull Device Enable Register (PERP) Read: Anytime. ...
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Port P Interrupt Enable Register (PIEP) Module Base + 0x001E PIEP7 PIEP6 W Reset 0 0 Figure 2-30. Port P Interrupt Enable Register (PIEP) Read: Anytime. Write: Anytime. Field 7–0 Pull Select Port P — This ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.5 Port J Registers 2.3.2.5.1 Port J I/O Register (PTJ) Module Base + 0x0028 PTJ7 PTJ6 W Reset Unimplemented or Reserved Read: Anytime. Write: Anytime. If ...
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Port J Data Direction Register (DDRJ) Module Base + 0x002A DDRJ7 DDRJ6 W Reset Unimplemented or Reserved Figure 2-34. Port J Data Direction Register (DDRJ) Read: Anytime. Write: Anytime. Field 7–6 Data Direction ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.5.5 Port J Pull Device Enable Register (PERJ) Module Base + 0x002C PERJ7 PERJ6 W Reset Unimplemented or Reserved Figure 2-36. Port J Pull Device Enable ...
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Port J Interrupt Enable Register (PIEJ) Module Base + 0x002E PIEJ7 PIEJ6 W Reset Unimplemented or Reserved Figure 2-38. Port J Interrupt Enable Register (PIEJ) Read: Anytime. Write: Anytime. Field 7–6 Interrupt Enable ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.6 Port AD Registers 2.3.2.6.1 Port AD I/O Register (PTAD) Module Base + 0x0030 PTAD7 PTAD6 W Reset 0 0 Read: Anytime. Write: Anytime. If the data direction bits ...
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Port AD Data Direction Register (DDRAD) Module Base + 0x0032 DDRAD7 DDRAD6 W Reset 0 0 Figure 2-42. Port AD Data Direction Register (DDRAD) Read: Anytime. Write: Anytime. Field 7–0 Data Direction Port AD — This ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.3.2.6.5 Port AD Pull Device Enable Register (PERAD) Module Base + 0x0034 PERAD7 PERAD6 W Reset 0 0 Figure 2-44. Port AD Pull Device Enable Register (PERAD) Read: Anytime. ...
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Functional Description Each pin can act as general purpose I/O. In addition the pin can act as an output from a peripheral module or an input to a peripheral module. A set of configuration registers is common to all ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description 2.4.1.4 Reduced Drive Register If the port is used as an output the register allows the configuration of the drive strength. 2.4.1.5 Pull Device Enable Register This register turns on a pull-up ...
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Port P The PWM module is connected to port P. Port P pins can be used as PWM outputs. Further the Keypad Wake-Up function is implemented on pins PP[7:0]. During reset, port P pins are configured as high- impedance ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description A valid edge on input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level directly or indirectly. The filters are continuously ...
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Port Data Direction T Input S Input M Input P Input J Input BKGD pin 2.6 Interrupts Port P and J generate a separate edge sensitive interrupt if enabled. 2.6.1 Interrupt Sources Table 2-40. Port Integration Module ...
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Chapter 2 Port Integration Module (PIM9C32) Block Description 108 MC9S12Q128 Rev 1.09 Freescale Semiconductor ...
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Chapter 3 Module Mapping Control (MMCV4) Block Description 3.1 Introduction This section describes the functionality of the module mapping control (MMC) sub-block of the S12 core platform. The block diagram of the MMC is shown in SECURE BDM_UNSECURE STOP, WAIT ...
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Chapter 3 Module Mapping Control (MMCV4) Block Description 3.1.1 Features • Registers for mapping of address space for on-chip RAM, EEPROM, and FLASH (or ROM) memory blocks and associated registers • Memory mapping control and selection based upon address decode ...
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Address Offset 0x0017 Reserved . . 0x001C Memory Size Register 0 (MEMSIZ0) 0x001D Memory Size Register 1 (MEMSIZ1 0x0030 Program Page Index Register (PPAGE) 0x0031 Reserved Freescale Semiconductor Chapter 3 Module Mapping Control (MMCV4) Block Description Table 3-1. ...
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Chapter 3 Module Mapping Control (MMCV4) Block Description 3.3.2 Register Descriptions Name Bit 7 0x0010 R RAM15 INITRM W 0x0011 R 0 INITRG W 0x0012 R EE15 INITEE W 0x0013 R 0 MISC W 0x0014 R Bit 7 MTSTO W ...
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Initialization of Internal RAM Position Register (INITRM) Module Base + 0x0010 Starting address location affected by INITRG register setting RAM15 RAM14 W Reset Unimplemented or Reserved Figure 3-3. Initialization of Internal RAM Position ...
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Chapter 3 Module Mapping Control (MMCV4) Block Description 3.3.2.2 Initialization of Internal Registers Position Register (INITRG) Module Base + 0x0011 Starting address location affected by INITRG register setting REG14 W Reset Unimplemented or ...
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Initialization of Internal EEPROM Position Register (INITEE) Module Base + 0x0012 Starting address location affected by INITRG register setting EE15 EE14 W 1 Reset — — 1. The reset state of this register is controlled at ...
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Chapter 3 Module Mapping Control (MMCV4) Block Description 3.3.2.4 Miscellaneous System Control Register (MISC) Module Base + 0x0013 Starting address location affected by INITRG register setting Reset: Expanded 0 or Emulation Reset: Peripheral 0 or Single ...
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Stretch Bit EXSTR1 3.3.2.5 Reserved Test Register 0 (MTST0) Module Base + 0x0014 Starting address location affected by INITRG register setting Reset Unimplemented or Reserved Figure 3-7. ...
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Chapter 3 Module Mapping Control (MMCV4) Block Description 3.3.2.7 Memory Size Register 0 (MEMSIZ0) Module Base + 0x001C Starting address location affected by INITRG register setting REG_SW0 0 W Reset — — = Unimplemented or Reserved Figure ...
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Table 3-9. Allocated RAM Memory Space (continued) Allocated ram_sw2:ram_sw0 RAM Space 011 8K bytes 100 10K bytes 101 12K bytes 110 14K bytes 111 16K bytes 1. The RAM Reset BASE Address is based on the reset value of the ...
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Chapter 3 Module Mapping Control (MMCV4) Block Description Field 7:6 Allocated System FLASH or ROM Physical Memory Space — The allocated system FLASH or ROM ROM_SW[1:0] physical memory space is as given in 1:0 Allocated Off-Chip FLASH or ROM Memory ...
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Program Page Index Register (PPAGE) Module Base + 0x0030 Starting address location affected by INITRG register setting Reset — — 1. The reset state of this register is controlled at chip integration. ...
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Chapter 3 Module Mapping Control (MMCV4) Block Description Table 3-14. Program Page Index Register Bits PIX5 PIX4 ...
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The MMC will make only one select signal active at any given time. This activation is based upon the priority outlined in Table ...
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Chapter 3 Module Mapping Control (MMCV4) Block Description unimplemented locations within the register space or to locations that are removed from the map (i.e., ports A and B in expanded modes) will not cause this signal to become active. When ...
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The PPAGE register holds the page select value for the program page window. The value of the PPAGE register can be manipulated by normal read and write (some devices don’t allow writes in some modes) instructions as well as the ...
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Chapter 3 Module Mapping Control (MMCV4) Block Description During the execution of an RTC instruction, the CPU: • Pulls the old PPAGE value from the stack • Pulls the 16-bit return address from the stack and loads it into the ...
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Table 3-20. 48K Byte Physical FLASH/ROM Allocated Address Space 0x0000–0x3FFF 0x4000–0x7FFF 0x8000–0xBFFF 0xC000–0xFFFF Table 3-21. 64K Byte Physical FLASH/ROM Allocated Address Space 0x0000–0x3FFF 0x4000–0x7FFF 0x8000–0xBFFF 0xC000–0xFFFF Freescale Semiconductor Chapter 3 Module Mapping Control (MMCV4) Block Description Page Window Access ROMHM ...
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Chapter 3 Module Mapping Control (MMCV4) Block Description A graphical example of a memory paging for a system configured as 1M byte on-chip FLASH/ROM with 64K allocated physical space is given in 0x0000 61 16K FLASH (UNPAGED) 0x4000 62 16K ...
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.1 Introduction This section describes the functionality of the multiplexed external bus interface (MEBI) sub-block of the S12 core platform. The functionality of the module is closely coupled with the S12 CPU and ...
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) REGS Addr[19:0] Data[15:0] (Control) CPU pipe info IRQ interrupt XIRQ interrupt BDM tag info Control signal(s) Data signal (unidirectional) Data signal (bidirectional) Data bus (unidirectional) Data bus (bidirectional) 130 ADDR ADDR EXT BUS ...
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Modes of Operation • Normal expanded wide mode Ports A and B are configured as a 16-bit multiplexed address and data bus and port E provides bus control and status signals. This mode allows 16-bit external memory and peripheral ...
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) . Table 4-1. External System Pins Associated With MEBI Pin Name Pin Functions BKGD/MODC/ MODC TAGHI BKGD TAGHI PA7/A15/D15/D7 PA7–PA0 thru A15–A8 PA0/A8/D8/D0 D15–D8 D15/D7 thru D8/D0 PB7/A7/D7 PB7–PB0 thru A7–A0 PB0/A0/D0 D7–D0 ...
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Table 4-1. External System Pins Associated With MEBI (continued) Pin Name Pin Functions PE4/ECLK PE4 ECLK PE3/LSTRB/ TAGLO PE3 LSTRB SZ8 TAGLO PE2/R/W PE2 R/W PE1/IRQ PE1 IRQ PE0/XIRQ PE0 XIRQ PK7/ECS PK7 ECS PK6/XCS PK6 XCS PK5/X19 PK5–PK0 thru ...
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.3.1 Module Memory Map Address Offset 0x0000 Port A Data Register (PORTA) 0x0001 Port B Data Register (PORTB) 0x0002 Data Direction Register A (DDRA) 0x0003 Data Direction Register B (DDRB) 0x0004 Reserved 0x0005 ...
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Read: Anytime when register is in the map Write: Anytime when register is in the map Port A bits 7 through 0 are associated with address lines A15 through A8 respectively and data lines D15/D7 through D8/D0 respectively. When this ...
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.3.2.3 Data Direction Register A (DDRA) Module Base + 0x0002 Starting address location affected by INITRG register setting Bit Reset 0 0 Figure 4-4. Data Direction Register ...
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Data Direction Register B (DDRB) Module Base + 0x0003 Starting address location affected by INITRG register setting Bit Reset 0 0 Figure 4-5. Data Direction Register B (DDRB) Read: Anytime when register is ...
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.3.2.5 Reserved Registers Module Base + 0x0004 Starting address location affected by INITRG register setting Reset Unimplemented or Reserved Module Base + 0x0005 Starting ...
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These register locations are not used (reserved). All unused registers and bits in this block return logic 0s when read. Writes to these registers have no effect. These registers are not in the on-chip map in special peripheral mode. 4.3.2.6 ...
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) To ensure that you read the value present on the PORTE pins, always wait at least one cycle after writing to the DDRE register before reading from the PORTE register. 4.3.2.7 Data Direction ...
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Port E Assignment Register (PEAR) Module Base + 0x000A Starting address location affected by INITRG register setting NOACCE W Reset Special Single Chip 0 Special Test 0 Peripheral 0 Emulation Expanded 1 Narrow Emulation Expanded 1 Wide ...
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) Field 7 CPU No Access Output Enable NOACCE Normal: write once Emulation: write never Special: write anytime 1 The associated pin (port E, bit 7) is general-purpose I/O. 0 The associated pin (port ...
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Mode Register (MODE) Module Base + 0x000B Starting address location affected by INITRG register setting MODC W Reset Special Single Chip 0 Emulation Expanded 0 Narrow Special Test 0 Emulation Expanded 0 Wide Normal Single Chip 1 ...
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) Field 7:5 Mode Select Bits — These bits indicate the current operating mode. MOD[C:A] If MODA = 1, then MODC, MODB, and MODA are write never. If MODC = MODA = 0, then ...
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Table 4-8. MODC, MODB, and MODA Write Capability MODC MODB MODA writes to the ...
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. These bits have no effect when the associated pin(s) are outputs. ...
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Field 7 Reduced Drive of Port K RDRK 0 All port K output pins have full drive enabled. 1 All port K output pins have reduced drive enabled. 4 Reduced Drive of Port E RDPE 0 All port E output ...
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.3.2.13 Reserved Register Module Base + 0x000F Starting address location affected by INITRG register setting Reset Unimplemented or Reserved This register location is not ...
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Port K Data Register (PORTK) Module Base + 0x0032 Starting address location affected by INITRG register setting Bit Reset 0 0 Alternate ECS XCS Pin Function Read: Anytime Write: Anytime This port is ...
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) 4.3.2.16 Port K Data Direction Register (DDRK) Module Base + 0x0033 Starting address location affected by INITRG register setting Bit Reset 0 0 Figure 4-20. Port K ...
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Table 4-15. Access Type vs. Bus Control Pins LSTRB 4.4.2 Stretched Bus Cycles In order to allow fast internal bus cycles to coexist in a system with slower external memory resources, the HCS12 supports the concept ...
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) There are two basic types of operating modes: 1. Normal modes: Some registers and bits are protected against accidental changes. 2. Special modes: Allow greater access to protected control registers and bits for ...
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Normal Expanded Wide Mode In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E bit 4 is configured as the E clock output signal. These signals allow external ...
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) The PE4/ECLK pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the ...
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Special Operating Modes There are two special operating modes that correspond to normal operating modes. These operating modes are commonly used in factory testing and system development. 4.4.3.2.1 Special Single-Chip Mode When the MCU is reset in this mode, ...
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) mode. Background debugging should not be used while the MCU is in special peripheral mode as internal bus conflicts between BDM and the external master can cause improper operation of both functions. 4.4.4 ...
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Chapter 5 Interrupt (INTV1) Block Description 5.1 Introduction This section describes the functionality of the interrupt (INT) sub-block of the S12 core platform. A block diagram of the interrupt sub-block is shown in WRITE DATA BUS INTERRUPTS XMASK IMASK RESET ...
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Chapter 5 Interrupt (INTV1) Block Description The interrupt sub-block decodes the priority of all system exception requests and provides the applicable vector for processing the exception. The INT supports I-bit maskable and X-bit maskable interrupts, a non- maskable unimplemented opcode ...
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External Signal Description Most interfacing with the interrupt sub-block is done within the core. However, the interrupt does receive direct input from the multiplexed external bus interface (MEBI) sub-block of the core for the IRQ and XIRQ pin data. ...
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Chapter 5 Interrupt (INTV1) Block Description Field 4 Write to the Interrupt Test Registers WRTINT Read: anytime Write: only in special modes and with I-bit mask and X-bit mask set. 0 Disables writes to the test registers; reads of the ...
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Field 7:0 Interrupt TEST Bits — These registers are used in special modes for testing the interrupt logic and priority INT[E:0] independent of the system configuration. Each bit is used to force a specific interrupt vector by writing it to ...
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Chapter 5 Interrupt (INTV1) Block Description 5.4.1 Low-Power Modes The INT does not contain any user-controlled options for reducing power consumption. The operation of the INT in low-power modes is discussed in the following subsections. 5.4.1.1 Operation in Run Mode ...
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Interrupt Priority Decoder The priority decoder evaluates all interrupts pending and determines their validity and priority. When the CPU requests an interrupt vector, the decoder will provide the vector for the highest priority interrupt request. Because the vector is ...
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Chapter 5 Interrupt (INTV1) Block Description 164 MC9S12Q128 Rev 1.09 Freescale Semiconductor ...
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Chapter 6 Background Debug Module (BDMV4) Block Description 6.1 Introduction This section describes the functionality of the background debug module (BDM) sub-block of the HCS12 core platform. A block diagram of the BDM is shown in HOST SYSTEM BKGD ENTAG ...
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Chapter 6 Background Debug Module (BDMV4) Block Description • Nine hardware commands using free cycles, if available, for minimal CPU intervention • Hardware commands not requiring active BDM • 15 firmware commands execute from the standard BDM firmware lookup table ...
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External Signal Description A single-wire interface pin is used to communicate with the BDM system. Two additional pins are used for instruction tagging. These pins are part of the multiplexed external bus interface (MEBI) sub-block and all interfacing between ...
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Chapter 6 Background Debug Module (BDMV4) Block Description 6.3 Memory Map and Register Definition A summary of the registers associated with the BDM is shown in host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands. Detailed descriptions of ...
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Register Descriptions Register Bit 7 Name 0xFF00 R X Reserved W 0xFF01 R ENBDM BDMSTS W 0xFF02 R X Reserved W 0xFF03 R X Reserved W 0xFF04 R X Reserved W 0xFF05 R X Reserved W 0xFF06 R CCR7 ...
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Chapter 6 Background Debug Module (BDMV4) Block Description 6.3.2.1 BDM Status Register (BDMSTS) 0xFF01 7 R ENBDM W Reset: (1) Special single-chip mode: 1 Special peripheral mode: 0 All other modes Note: 1. ENBDM is read as "1" ...
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Field 7 Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made ENBDM active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM hardware ...
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Chapter 6 Background Debug Module (BDMV4) Block Description Table 6-2. BDMSTS Field Descriptions (continued) Field 2 Clock Switch — The CLKSW bit controls which clock the BDM operates with only writable from a hardware CLKSW BDM command. A ...
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BDM CCR Holding Register (BDMCCR) 0xFF06 CCR7 CCR6 W Reset 0 0 Figure 6-4. BDM CCR Holding Register (BDMCCR) Read: All modes Write: All modes When BDM is made active, the CPU stores the value of ...
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Chapter 6 Background Debug Module (BDMV4) Block Description 6.4 Functional Description The BDM receives and executes commands from a host via a single wire serial interface. There are two types of BDM commands, namely, hardware commands and firmware commands. Hardware ...
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BDM becomes active before or after execution of the next instruction attempt is made to activate BDM before being enabled, the CPU resumes normal instruction execution after a brief delay. ...
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Chapter 6 Background Debug Module (BDMV4) Block Description The BDM hardware commands are listed in Opcode Command (hex) BACKGROUND 90 ACK_ENABLE D5 ACK_DISABLE D6 READ_BD_BYTE E4 READ_BD_WORD EC READ_BYTE E0 READ_WORD E8 WRITE_BD_BYTE C4 WRITE_BD_WORD CC WRITE_BYTE C0 WRITE_WORD C8 ...
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The standard BDM firmware watches for serial commands and executes them as they are received. The firmware commands are shown in (1) Command Opcode (hex) READ_NEXT 62 16-bit data out READ_PC 63 16-bit data out READ_D 64 16-bit data ...
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Chapter 6 Background Debug Module (BDMV4) Block Description 16-bit misaligned reads and writes are not allowed. If attempted, the BDM will ignore the least significant bit of the address and will assume an even address from the remaining bits. For ...
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BITS AT 16 TC/BIT HARDWARE COMMAND READ HARDWARE COMMAND WRITE 44-BC DELAY FIRMWARE COMMAND READ FIRMWARE COMMAND WRITE 64-BC DELAY GO, COMMAND TRACE 6.4.6 BDM Serial Interface The BDM communicates with external devices serially via the BKGD pin. During ...
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Chapter 6 Background Debug Module (BDMV4) Block Description earlier. Synchronization between the host and target is established in this manner at the start of every bit time. Figure 6-7 shows an external host transmitting a logic 1 and transmitting a ...
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CLOCK TARGET SYSTEM HOST DRIVE TO BKGD PIN TARGET SYSTEM SPEEDUP PULSE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME BKGD PIN Figure 6-8. BDM Target-to-Host Serial Bit Timing (Logic 1) Figure 6-9 shows the host receiving a logic 0 from the ...
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Chapter 6 Background Debug Module (BDMV4) Block Description 6.4.7 Serial Interface Hardware Handshake Protocol BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Because the BDM clock source can be asynchronously related to the bus ...
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Figure 6-11 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the address of the memory location to ...
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Chapter 6 Background Debug Module (BDMV4) Block Description 6.4.8 Hardware Handshake Abort Procedure The abort procedure is based on the SYNC command. In order to abort a command, which had not issued the corresponding ACK pulse, the host controller should ...
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READ_BYTE CMD IS ABORTED BY THE SYNC REQUEST BKGD PIN READ_BYTE MEMORY ADDRESS HOST TARGET AND STARTS TO EXECUTES THE READ_BYTE CMD Figure 6-12. ACK Abort Procedure at the Command Level Figure 6-13 shows a conflict between the ACK pulse ...
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Chapter 6 Background Debug Module (BDMV4) Block Description The commands are described as follows: • ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse when a CPU command is executed by the CPU. The ACK_ENABLE ...
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SYNC — Request Timed Reference Pulse The SYNC command is unlike other BDM commands because the host does not necessarily know the correct communication speed to use for BDM communications until after it has analyzed the response to the ...
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Chapter 6 Background Debug Module (BDMV4) Block Description If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. Upon return to standard BDM firmware execution, the program counter ...
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If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the command to be disregarded. The data is not available for retrieval after the time-out has occurred. This ...
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Chapter 6 Background Debug Module (BDMV4) Block Description 190 MC9S12Q128 Rev 1.09 Freescale Semiconductor ...
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Chapter 7 Debug Module (DBGV1) Block Description 7.1 Introduction This section describes the functionality of the debug (DBG) sub-block of the HCS12 core platform. The DBG module is designed to be fully compatible with the existing BKP_HCS12_A module (BKP mode) ...
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Chapter 7 Debug Module (DBGV1) Block Description The DBG in DBG mode includes these distinctive features: • Three comparators (A, B, and C) — Dual mode, comparators A and B used to compare addresses — Full mode, comparator A compares ...
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Data associated with event B trigger modes — Detail report mode stores address and data for all cycles except program (P) and free (f) cycles — Current instruction address when in profiling mode — BGND is not considered a ...
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Chapter 7 Debug Module (DBGV1) Block Description CLOCKS AND CONTROL SIGNALS . . . . . . EXPANSION ADDRESS ADDRESS WRITE DATA READ DATA REGISTER BLOCK BKPCT0 BKPCT1 BKP READ BKP0X DATA BUS WRITE BKP0H DATA BUS BKP0L BKP1X BKP1H ...
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DBG READ DATA BUS ADDRESS BUS WRITE DATA BUS READ DATA BUS READ/WRITE DBG MODE ENABLE CHANGE-OF-FLOW INDICATORS MCU IN BDM CPU PROGRAM COUNTER INSTRUCTION LAST CYCLE REGISTER BUS CLOCK WRITE DATA BUS M U READ DATA BUS X READ/WRITE ...
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Chapter 7 Debug Module (DBGV1) Block Description 7.3 Memory Map and Register Definition A summary of the registers associated with the DBG sub-block is shown in descriptions of the registers and bits are given in the subsections that follow. 7.3.1 ...
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Name Bit 7 R Bit 15 0x0022 DBGTBH W R Bit 7 0x0023 DBGTBL W R TBF 0x0024 DBGCNT W R 0x0025 PAGSEL ((2)) DBGCCX W R 0x0026 Bit 15 (2) DBGCCH W R 0x0027 Bit 7 (2) DBGCCL ...
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Chapter 7 Debug Module (DBGV1) Block Description 1. The DBG module is designed for backwards compatibility to existing BKP modules. Register and bit names have changed from the BKP module. This column shows the DBG register name, as well as ...
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Table 7-3. DBGC1 Field Descriptions (continued) Field 3 DBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint based DBGBRK on comparator A and B to the CPU upon completion of a tracing session. ...
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Chapter 7 Debug Module (DBGV1) Block Description 7.3.2.2 Debug Status and Control Register (DBGSC) Module Base + 0x0021 Starting address location affected by INITRG register setting Reset Unimplemented or Reserved Figure ...