MC74HC4046N Motorola, MC74HC4046N Datasheet

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MC74HC4046N

Manufacturer Part Number
MC74HC4046N
Description
Phase Locked Loop
Manufacturer
Motorola
Datasheet
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Phase-Locked Loop
High–Performance Silicon–Gate CMOS
CMOS device. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL outputs.
voltage–controlled oscillator (VCO) and unity gain op–amp DEM OUT . The
comparators have two common signal inputs, COMP IN , and SIG IN . Input
SIG IN and COMP IN can be used directly coupled to large voltage signals, or
indirectly coupled (with a series capacitor to small voltage signals). The
self–bias circuit adjusts small voltage signals in the linear region of the
amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error
signal PC1 OUT and maintains 90 degrees phase shift at the center
frequency between SIG IN and COMP IN signals (both at 50% duty cycle).
Phase comparator 2 (with leading–edge sensing logic) provides digital error
signals PC2 OUT and PCP OUT and maintains a 0 degree phase shift
between SIG IN and COMP IN signals (duty cycle is immaterial). The linear
VCO produces an output signal VCO OUT whose frequency is determined by
the voltage of input VCO IN signal and the capacitor and resistors connected
to pins C1A, C1B, R1 and R2. The unity gain op–amp output DEM OUT with
an external resistor is used where the VCO IN signal is needed but no loading
can be tolerated. The inhibit input, when high, disables the VCO and all
op–amps to minimize standby power consumption.
cy synthesis and multiplication, frequency discrimination, tone decoding,
data synchronization and conditioning, voltage–to–frequency conversion
and motor speed control.
10/95
Motorola, Inc. 1995
The MC574HC4046A is similar in function to the MC14046 Metal gate
The HC4046A phase–locked loop contains three phase comparators, a
Applications include FM and FSK modulation and demodulation, frequen-
Output Drive Capability: 10 LSTTL Loads
Low Power Consumption Characteristic of CMOS Devices
Operating Speeds Similar to LSTTL
Wide Operating Voltage Range: 3.0 to 6.0 V
Low Input Current: 1.0 A Maximum (except SIG IN and COMP IN )
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Low Quiescent Current: 80 A Maximum (VCO disabled)
High Noise Immunity Characteristic of CMOS Devices
Diode Protection on all Inputs
Chip Complexity: 279 FETs or 70 Equivalent Gates
Pin No.
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
DEM OUT
VCO OUT
PCP OUT
PC1 OUT
PC2 OUT
PC3 OUT
COMP IN
Symbol
VCO IN
SIG IN
GND
V CC
C1A
C1B
INH
R1
R2
Phase Comparator Pulse Output
Phase Comparator 1 Output
Comparator Input
VCO Output
Inhibit Input
Capacitor C1 Connection A
Capacitor C1 Connection B
Ground (0 V) V SS
VCO Input
Demodulator Output
Resistor R1 Connection
Resistor R2 Connection
Phase Comparator 2 Output
Signal Input
Phase Comparator 3 Output
Positive Supply Voltage
Name and Function
3–1
REV 6
16
MC74HC4046A
16
COMP in
VCO out
PCP out
1
PC1 out
ORDERING INFORMATION
MC74HCXXXXAN
MC74HCXXXXAD
GND
C1A
C1B
INH
1
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
PLASTIC PACKAGE
SOIC PACKAGE
16
15
14
13
12
10
11
CASE 751B–05
9
CASE 648–08
N SUFFIX
D SUFFIX
Plastic
SOIC
V CC
PC3 out
SIG in
PC2 out
R2
R1
DEM out
VCO in

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MC74HC4046N Summary of contents

Page 1

... R2 Resistor R2 Connection 13 PC2 OUT Phase Comparator 2 Output 14 SIG IN Signal Input 15 PC3 OUT Phase Comparator 3 Output Positive Supply Voltage 10/95 Motorola, Inc. 1995 16 Name and Function 3–1 REV 6 MC74HC4046A N SUFFIX PLASTIC PACKAGE CASE 648– SUFFIX SOIC PACKAGE 16 CASE 751B–05 1 ORDERING INFORMATION ...

Page 2

... Plastic DIP: – from 125 _ C SOIC Package: – from 125 _ C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 3

... Current (per Package) (VCO disabled) Pins 3, 5 and Pin 9 at GND; Input Leakage at Pins 3 and excluded NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). [Phase Comparator Section] AC ELECTRICAL CHARACTERISTICS Symbol Symbol Parameter ...

Page 4

... INH, VCO IN V VCO IN Operating Voltage Range at INH = V IL VCO IN over the range specified for R1; For linearity see Fig. 15A, Parallel value of R1 and R2 should be > 2 Resistor Range R2 C1 Capacitor Range MOTOROLA (Voltages Referenced to GND – Volts Volts Test Conditions Test Conditions 3 4.5 6 ...

Page 5

... MC74HC4046A Guaranteed Limit 85 C 125 C Max Min Max Min Max Unit Unit Unit %/K MHz See Figures 15A Typical 50% % Guaranteed Limit 85 C 125 C Unit Unit Unit Max Min Max Min Max 300 k 300 300 See Figure 12 mV Typical 25 MOTOROLA ...

Page 6

... PCP OUT , PC1 OUT 50% PC3 OUT OUTPUTS 10% t THL Figure 1. SIG IN 50% INPUT COMP IN 50% INPUT t PLZ t PZL 50% PC2 OUT OUTPUT 10% Figure 3. MOTOROLA SWITCHING WAVEFORMS SIG 50% INPUT GND COMP IN t PLH INPUT t PZH PC2 OUT 50% OUTPUT t TLH V CC GND V CC DEVICE UNDER ...

Page 7

... Op–amps (see Figure 5). This is useful if the internal VCO is not being used. A logic high on inhibit disables the VCO and all Op–amps, minimizing standby power consump- tion CURRENT MIRROR (EXTERNAL ref + + Figure 5. Logic Diagram for VCO 3–7 MC74HC4046A 4 VCO OUT MOTOROLA ...

Page 8

... In order to achieve lock when the PLL input frequency increases, the MOTOROLA COMP IN . The SIG IN and COMP IN have a special DC bias network that enables AC coupling of input signals. If the sig- nals are not AC coupled, standard 54HC/74HC input levels are required ...

Page 9

... SIG IN COMP IN PC2 OUT HIGH IMPEDANCE OFF–STATE VCO IN PCP OUT Figure 8. Typical Waveforms for PLL Using Phase Comparator 2 SIG IN COMP IN PC3 OUT VCO IN Figure 9. Typical Waveform for PLL Using Phase Comparator 3 3–9 MC74HC4046A V CC GND VCC GND MOTOROLA ...

Page 10

... 4 100 pF VCOIN = 1 –15 –100 – AMBIENT TEMPERATURE ( C) Figure 13B. Frequency Stability versus Ambient Temperature 4.5 V MOTOROLA V CC =3 =6 +1.0 V –4.0 1/2V CC – 500 mV Figure 11. Input Current at SIG IN , COMP IN with 500 mV at Self–Bias Point ...

Page 11

... Figure 15B. Definition of VCO Frequency Linearity 3–11 MC74HC4046A 0.1 F 1.0 1.5 2.0 2.5 3.0 3.5 V VCOIN ( 300 0.1 F 1.0 1.5 2.0 2.5 3.0 3.5 4.0 V VCOIN (V) MIN 1 MAX V = 0.5 V OVER THE V CC RANGE: FOR VCO LINEARITY LINEARITY = (f 0 – 100% MOTOROLA 4.0 4.5 ...

Page 12

... VCOIN = 1 FOR 4.5 V AND 6 VCOIN = 1 FOR 3.0 V; INH = GND; T amb = 4.5 V 3 4.5 V 3 4 (pF) Figure 20. Frequency Offset versus C1 MOTOROLA pF VCOIN = amb = Figure 17. Power Dissipation versus 6 3.0 V 6 ...

Page 13

... Figure 24. R2 versus Frequency Lock Range ( High–Speed CMOS Logic Data DL129 — Rev 8.0 6.0 4.0 2.0 0 –2 C1= 3–13 MC74HC4046A C1=39 pF R1=3 k R1=10 k R1=20 k R1=30 k R1=40 k R1=50 k R1=100 k R1=300 Figure 23. R2 versus f min R1=10 k R1=3.0 k R1=20 k R1=30 k R1=40 k R1=50 k R1=100 k R1=300 MOTOROLA ...

Page 14

... Determine R1–C1 from Figure 21. Calculate value of R1 from the value of C1 and the product of R1C1 from Figure 21. (see Figure 24 for characteristics of the VCO operation) MOTOROLA Phase Comparator Given f max and f0 Given f0 and fL Determine the Calculate f min value of R1 and f min = f0–fL ...

Page 15

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “ ...

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