MC68HC11K1CFU4 Motorola, MC68HC11K1CFU4 Datasheet

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MC68HC11K1CFU4

Manufacturer Part Number
MC68HC11K1CFU4
Description
8-Bit Microcontroller MC68HC11K1CFU4Technical Summary 8-Bit Microcontroller
Manufacturer
Motorola
Datasheet

Specifications of MC68HC11K1CFU4

Case
QFP

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M68HC11K/D
M68HC11K Family
Technical Data
HCMOS
Microcontroller Unit

Related parts for MC68HC11K1CFU4

MC68HC11K1CFU4 Summary of contents

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M68HC11K/D M68HC11K Family Technical Data HCMOS Microcontroller Unit ...

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blank ...

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... Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...

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... The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Technical Data 4 Revision History Revision Date Level October, 2001 N/A Page Description Number(s) Original release N/A M68HC11K Family MOTOROLA ...

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... Section 10. Analog-to-Digital (A/D) Converter . . . . . . . 221 Section 11. Memory Expansion Section 12. Electrical Characteristics . . . . . . . . . . . . . . 253 Section 13. Mechanical Data . . . . . . . . . . . . . . . . . . . . . 273 Section 14. Ordering Information . . . . . . . . . . . . . . . . . 281 Section 15. Development Support . . . . . . . . . . . . . . . . . 283 Index 285 M68HC11K Family MOTOROLA and On-Chip Memory . . . . . . . . . . . . . . . . . . . 63 Interface (SCI 149 and Chip Selects 231 List of Sections List of Sections Technical Data 5 ...

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... List of Sections Technical Data 6 List of Sections M68HC11K Family MOTOROLA ...

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... M68HC11K Family MOTOROLA Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 M68HC11K Family Members . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Section 2. Pin Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power Supply ( Reset (RESET Crystal Driver and External Clock Input (XTAL and EXTAL XOUT ...

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... Stack Pointer (SP Program Counter (PC .50 Condition Code Register (CCR Carry/Borrow ( Overflow ( Zero ( .50 Negative ( Interrupt Mask ( Half Carry ( .51 Non-Maskable Interrupt ( Stop Disable ( Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Immediate Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Indexed Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Instruction Set .55 Table of Contents M68HC11K Family MOTOROLA ...

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... M68HC11K Family MOTOROLA Section 4. Operating Modes and On-Chip Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Single-Chip Mode Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Special Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Mode Selection Memory Map Control Registers and RAM ...

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... Non-Maskable Interrupt Request (XIRQ 120 Illegal Opcode Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Software Interrupt (SWI 121 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Reset and Interrupt Priority 122 Reset and Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . .123 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 Slow Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 Table of Contents M68HC11K Family MOTOROLA ...

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... M68HC11K Family MOTOROLA Section 6. Parallel Input/Output Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Port 138 Port 139 Port 140 Port 142 Port 143 Port 144 Port 145 Port 146 Internal Pullup Resistors 147 Section 7 ...

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... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Timer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Input Capture and Output Compare Overview . . . . . . . . . . . . 185 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Timer Interrupt Flag 2 Register . . . . . . . . . . . . . . . . . . . . . 189 Timer Interrupt Mask 2 Register 189 Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . . 190 Pulse Accumulator Control Register . . . . . . . . . . . . . . . . . 191 Table of Contents M68HC11K Family MOTOROLA ...

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... M68HC11K Family MOTOROLA Input Capture (IC 191 Timer Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . 192 Timer Input Capture 4/Output Compare 5 Register . . . . . . 193 Timer Interrupt Flag 1 Register . . . . . . . . . . . . . . . . . . . . . 194 Timer Interrupt Mask 1 Register 194 Timer Control 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Output Compare (OC 196 Timer Output Compare Registers ...

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... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 Memory Size and Address Line Allocation 232 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 Port G Assignment Register . . . . . . . . . . . . . . . . . . . . . 234 Memory Mapping Size Register . . . . . . . . . . . . . . . . . . .235 Memory Mapping Window Base Register . . . . . . . . . . . 236 Memory Mapping Window Control Registers .237 Table of Contents M68HC11K Family MOTOROLA ...

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... Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . 265 12.11 Expansion Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 12.12 Serial Peripheral Interface Timing . . . . . . . . . . . . . . . . . . . . . 269 12.13 EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 M68HC11K Family MOTOROLA Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Program Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Input/Output Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . 241 General-Purpose Chip Selects 242 Memory Mapping Size Register . . . . . . . . . . . . . . . . . . .243 General-Purpose Chip Select 1 Address Register ...

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... J-Cerquad (Case 780A .276 80-Pin Quad Flat Pack (Case 841B 277 80-Pin Low-Profile Quad Flat Pack (Case 917A 278 68-Pin Plastic Leaded Chip Carrier (Case 779 279 68-Pin J-Cerquad (Case 779A .280 Section 14. Ordering Information Section 15. Development Support Index Table of Contents M68HC11K Family MOTOROLA ...

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... Block Protect Register (BPROT 4-11 System Configuration Options Register (OPTION 4-12 Block Protect Register (BPROT 100 M68HC11K Family MOTOROLA Title M68HC11K4 Family Block Diagram . . . . . . . . . . . . . . . . . . . . . 29 M68HC11KS Family Block Diagram Pin Assignments for M68HC11K 84-Pin PLCC/J-Cerquad . . . 32 Pin Assignments for M6811K 80-Pin QFP . . . . . . . . . . . . . . . . 33 Pin Assignments for M6811KS 68-Pin PLCC/J-Cerquad ...

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... Port B Data Register (PORTB 139 Port B Data Direction Register (DDRB 139 Port C Data Register (PORTC 140 Port C Data Direction Register (DDRC 141 System Configuration Options 2 Register (OPT2 .141 Port D Data Register (PORTD 142 Port D Data Direction Register (DDRD 142 List of Figures Page M68HC11K Family MOTOROLA ...

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... Timer Interrupt Flag 1 Register (TFLG1 194 9-11 Timer Interrupt Mask 1 Register (TMSK1 194 9-12 Timer Control 2 Register (TCTL2 195 M68HC11K Family MOTOROLA Title SCI Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 SCI Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . .152 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 155 SCI Baud Generator Circuit Diagram . . . . . . . . . . . . . . . . . . .157 SCI Baud Rate Control Register High (SCBDH) ...

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... Technical Data 20 Title Registers (TOC1–TOC4 197 Compare 5 Register (TI4/O5 199 Polarity Register (PWPOL 215 Prescaler Register (PWSCAL 215 Enable Register (PWEN 216 Counters (PWCNT1 to PWCNT4 .217 Periods (PWPER1 to PWPER4 218 Duty Cycle (PWDTY1 to PWDTY4 219 List of Figures Page M68HC11K Family MOTOROLA ...

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... Memory Expansion Example 1 — Memory Map 11-16 Memory Expansion Example 2 Memory Map 12-1 Test Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 12-2 Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 M68HC11K Family MOTOROLA Title Registers (MM1CR and MM2CR 237 Address Register (GPCS1A .243 Control Register (GPCS1C 244 Address Register (GPCS2A .245 Control Register (GPCS2C) ...

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... WAIT Recovery from Inerrupt Timing Diagram 262 12-6 Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 12-7 Port Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 12-8 Port Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 12-9 Expansion Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 12-10 SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 Technical Data 22 Title List of Figures Page M68HC11K Family MOTOROLA ...

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... M68HC11K Family MOTOROLA Title M68HC11K Family Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 I/O Ports and Peripheral Functions Port Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Instruction Set .56 Registers with Limited Write Access Synchronization Character Selection . . . . . . . . . . . . . . . . . . . . 79 Hardware Mode Select Summary Default Memory Map Addresses . . . . . . . . . . . . . . . . . . . . . . . 83 RAM Mapping ...

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... Main Timer Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Timer Prescale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Input Capture Edge Selection 195 Timer Output Compare Actions . . . . . . . . . . . . . . . . . . . . . . .201 Pulse Accumulator Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Pulse Accumulator Edge Control . . . . . . . . . . . . . . . . . . . . . . 206 Real-Time Interrupt Rate versus RTR[1: 210 Clock A Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Clock B Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 List of Tables Page M68HC11K Family MOTOROLA ...

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... ROM with: • • • • Custom-ROM devices have a ROM array that is programmed at the factory to customer specifications. M68HC11K Family MOTOROLA Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 M68HC11K Family Members . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Disabled ROM Disabled EEPROM (electrically erasable, programmable read-only memory) ...

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... Yes 1 K 640 640 51 No General Description Slow Packages Mode No (2) 84-pin PLCC No (3) 80-pin QFP No (4) 84-pin J-cerquad No 84-pin PLCC 80-pin QFP Yes 68-pin PLCC and 80-pin LQFP 68-pin J-cerquad, 68-pin PLCC, Yes and 80-pin LQFP M68HC11K Family MOTOROLA (5) ...

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... M68HC11K Family MOTOROLA 8-bit opcodes and data 16-bit addressing Two 8-bit accumulators, which can be concatenated to form one 16-bit accumulator On-board memory: – 24 Kbytes or 32 Kbytes of ROM, EPROM, or OTPROM – 768 bytes or 1 Kbyte of static RAM (random-access memory) – ...

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... J-cerquad (ceramic windowed version of PLCC) 84-pin plastic leaded chip carrier (PLCC) – KS versions: 68-pin J-cerquad (ceramic windowed version of PLCC) 80-pin low-profile quad flat pack (LQFP) 68-pin plastic leaded chip carrier (PLCC) General Description M68HC11K Family MOTOROLA ...

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... ADDRESS BUS DDRB PORT B Notes: 1. XOUT pin omitted on 80-pin QFP 2. V applies only to EPROM devices. PP Figure 1-1. M68HC11K4 Family Block Diagram M68HC11K Family MOTOROLA is a block diagram of the M68HC11K Family MCU block diagram of the M68HC11KS devices. MODB/ V LIR STBY EXTAL XTAL E ...

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... AN7 PE6 AN6 PE5 AN5 A/D PE4 AN4 CONVERTER PE3 AN3 PE2 AN2 PE1 AN1 PE0 AN0 PD5 SS PD4 SCK SPI PD3 MOSI PD2 MISO PD1 TxD SCI PD0 RxD 640 BYTES EEPROM PWMs DDRG DDRH PORT G PORT H M68HC11K Family MOTOROLA ...

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... Introduction The M68HC11K Family is available in a variety of packages, as shown in Table 1-1. M68HC11K Family two or more functions, as described in this section. Pin assignments for the various package types are shown in Figure M68HC11K Family MOTOROLA Section 2. Pin Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power Supply ( Reset (RESET Crystal Driver and External Clock Input (XTAL and EXTAL) ...

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... Pins 20, 22, and 25 are used only during factory testing and should not be connected to external circuitry applies only to EPROM devices. PP Figure 2-1. Pin Assignments for M68HC11K 84-Pin PLCC/J-Cerquad Technical Data 32 Pin Description 74 PD2/MISO 73 PD1 PD0 MODA/LIR 70 MODB/V STBY 69 RESET 68 XTAL 67 EXTAL 66 XOUT PC7/DATA7 61 PC6/DATA6 60 PC5/DATA5 59 PC4/DATA4 58 PC3/DATA3 57 PC2/DATA2 56 PC1/DATA1 55 PC0/DATA0 54 IRQ M68HC11K Family MOTOROLA ...

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... PA3/IC4/OC5/OC1 8 PA2/IC1 9 PA1/IC2 10 PA0/IC3 PB7/ADDR15 14 PB6/ADDR14 15 PB5/ADDR13 16 PB4/ADDR12 17 PB3/ADDR11 18 PB2/ADDR10 19 PB1/ADDR9 applies only to EPROM devices. PP Figure 2-2. Pin Assignments for M6811K 80-Pin QFP M68HC11K Family MOTOROLA Pin Description Pin Description Introduction 60 PF0/ADDR0 59 PF1/ADDR1 58 PF2/ADDR2 57 PF3/ADDR3 56 PF4/ADDR4 55 PF5/ADDR5 54 PF6/ADDR6 53 PF7/ADDR7 PE0/AN0 48 PE1/AN1 ...

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... PH3/PW4 21 XIRQ PG7/R/W 23 IRQ PE7/AN7 applies only to EPROM devices. PP Figure 2-3. Pin Assignments for M6811KS 68-Pin PLCC/J-Cerquad Technical Data Pin Description MODA/LIR MODB/V STBY RESET XTAL EXTAL XOUT E PC7/DATA7 PC6/DATA6 PC5/DATA5 PC4/DATA4 PC3/DATA3 PC2/DATA2 PC1/DATA1 PC0/DATA0 PF0/ADDR0 PF1/ADDR1 M68HC11K Family MOTOROLA ...

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... PD4/SCK 5 PD5/ PA7/PAI/OC1 14 PA6/OC2/OC1 15 PA5/OC3/OC1 16 PA4/OC4/OC1 17 PA3/IC4/OC5/OC1 18 PA2/IC1 19 PA1/IC2 20 PA0/IC3 * V applies only to EPROM devices. PP Figure 2-4. Pin Assignments for M6811KS 80-Pin LQFP M68HC11K Family MOTOROLA Pin Description Pin Description Introduction 60 PF2/ADDR2 59 PF3/ADDR3 58 PF4/ADDR4 57 PF5/ADDR5 56 PF6/ADDR6 55 PF7/ADDR7 PE0/AN0 47 PE1/AN1 46 PE2/AN2 45 PE3/AN3 44 PE4/AN4 ...

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... To prevent the device from misinterpreting the kind of reset that occurs, do not connect an external resistor-capacitor (RC) power-up delay circuit directly to the reset pin. Technical Data and ground. There are three V SS Pin Description and AV , for the DD SS M68HC11K Family MOTOROLA ...

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... EXTAL pin, the XTAL pin must be left unterminated. CAUTION: In all cases, use caution around the oscillator pins. Load capacitances shown in manufacturer and should include all stray layout capacitances. M68HC11K Family MOTOROLA Crystal Driver and External Clock Input (XTAL and EXTAL 4.7 k 1.0 ...

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... I bit in the condition code register (CCR), which can be set or cleared by software at any time. Triggering is level sensitive by default, which is Technical Data 38 EXTAL MCU 10 M XTAL * This value includes all stray capacitances. Figure 2-6. Common Crystal Connections 4.9 XOUT Pin Pin Description CRYSTAL Control. M68HC11K Family MOTOROLA ...

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... Mode Selection, Instruction Cycle Reference, and Standby Power (MODA/LIR and MODB/V During reset, MODA and MODB select one of four operating modes: 1. Single-chip 2. Expanded 3. Bootstrap 4. Special test For full descriptions of these modes, refer to M68HC11K Family MOTOROLA Interrupts. , during EPROM or OTPROM programming STBY Pin Description Pin Description during normal DD 4 ...

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... INSTRUCTION E OPCODE FETCH LIR Note: If LIRDV is not set, the pullup resistor may Figure 2-8. LIR Timing Pin Description through a 4.7-k pullup resistor Bit 0 LSBF SPR2 XDV1 XDV0 not return the level to a logic 1 before the next data fetch. M68HC11K Family MOTOROLA 0 ...

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... The K series contains 62 input/output lines arranged in eight ports, A through H; all ports are eight bits except port D, which is six bits. The KS series drops seven lines from port G and four from port H, for a total of M68HC11K Family MOTOROLA When V STBY. has been restored to a valid level. The extra hardware required ...

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... Expanded Section 4. Operating Modes and On-Chip Memory operating modes and Section 11. Memory Expansion and Chip Selects (2) control registers Section 9. Timing System Control registers Section 11. Memory Expansion and Chip Selects Pin Description Section 6. Parallel Refer to and and and M68HC11K Family MOTOROLA ...

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... M68HC11K Family MOTOROLA Table 2-2. Port Signal Summary Single-Chip and Port/Bit Bootstrap Modes PA0 PA0/IC3 PA1 PA1/IC2 PA2 PA2/IC1 PA3 PA3/OC5/IC4/and-or OC1 PA4 PA4/OC4/and-or OC1 PA5 PA5/OC3/and-or OC1 PA6 PA6/OC2/and-or OC1 PA7 PA7/PAI/and-or OC1 PB[7:0] PB[7:0] PC[7:0] PC[7:0] PD0 PD0/RxD PD1 ...

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... Pin Description Technical Data 44 Pin Description M68HC11K Family MOTOROLA ...

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... M68HC11K Family MOTOROLA Section 3. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Accumulators A, B, and D (ACCA, ACCB, and ACCD Index Register X (IX Index Register Y (IY Stack Pointer (SP Program Counter (PC .50 Condition Code Register (CCR Carry/Borrow (C) ...

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... OR 16-BIT DOUBLE ACCUMULATOR D IX INDEX REGISTER X IY INDEX REGISTER Y SP STACK POINTER PC PROGRAM COUNTER CONDITION CODES CARRY/BORROW FROM MSB OVERFLOW ZERO NEGATIVE I-INTERRUPT MASK HALF CARRY (FROM BIT 3) X-INTERRUPT MASK STOP DISABLE Figure 3-1. Programming Model Central Processor Unit (CPU) M68HC11K Family MOTOROLA ...

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... M68HC11K Family MOTOROLA The ABX and ABY instructions add the contents of 8-bit accumulator B to the contents of 16-bit register but there are no equivalent instructions that use A instead of B. ...

Page 48

... A, and pull accumulator A off the stack just before leaving the subroutine, to ensure that the contents of that register will be the same after returning from the subroutine as it was before starting the subroutine. Technical Data 48 Figure 3-2 Central Processor Unit (CPU summary of SP M68HC11K Family MOTOROLA ...

Page 49

... BSR, BRANCH TO SUBROUTINE MAIN PROGRAM PC SP–2 $8D = BSR SP–1 RTS, RETURN FROM SUBROUTINE MAIN PROGRAM PC $39 = RTS SP+1 SP+2 M68HC11K Family MOTOROLA RTI, RETURN FROM INTERRUPT STACK 7 0 SP–2 SP–1 RTN H RTN SP L SWI, SOFTWARE INTERRUPT WAI, WAIT FOR INTERRUPT STACK ...

Page 50

... The Z bit is set if the result of an arithmetic, logic, or data manipulation operation is 0. Otherwise, the Z bit is cleared. Compare instructions do Technical Data 50 5.3 Sources of Resets. Five condition code indicators ( and H) Two interrupt masking bits (IRQ and XIRQ) A stop disable bit (S) Table 3-1 Central Processor Unit (CPU) shows which condition M68HC11K Family MOTOROLA ...

Page 51

... The H bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic unit during an ADD, ABA, or ADC instruction. Otherwise, the H bit is cleared. Half carry is used during binary-coded decimal (BCD) operations. M68HC11K Family MOTOROLA Section 5. Resets and Interrupts. Central Processor Unit (CPU) Central Processor Unit (CPU) ...

Page 52

... Because the M68HC11 is an 8-bit CPU, Technical Data 52 Bit data 8-bit and 16-bit signed and unsigned integers 16-bit unsigned fractions 16-bit addresses Central Processor Unit (CPU) M68HC11K Family MOTOROLA ...

Page 53

... The effective address can be specified within an instruction or it can be calculated. M68HC11K Family MOTOROLA Central Processor Unit (CPU) Central Processor Unit (CPU) Opcodes and Operands Technical Data ...

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... IY). Any memory location in the 64-Kbyte address space can be accessed with this mode. The instructions are from two to five bytes. Technical Data 54 Central Processor Unit (CPU) M68HC11K Family MOTOROLA ...

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... These are usually 2-byte instructions. 3.7 Instruction Set Table 3-1 all possible addressing modes. M68HC11K Family MOTOROLA Control instructions with no arguments Operations that only involve the index registers or accumulators presents a detailed listing of all the M68HC11 instructions in Central Processor Unit (CPU) Central Processor Unit (CPU) ...

Page 56

... M68HC11K Family MOTOROLA C — — — — — — — ...

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... Clear Memory 0 Byte CLRA Clear 0 Accumulator A CLRB Clear 0 Accumulator B CLV Clear Overflow 0 Flag CMPA (opr) Compare – M Memory CMPB (opr) Compare – M Memory M68HC11K Family MOTOROLA Addressing Instruction Mode Opcode REL REL REL 2E REL 22 REL 24 A IMM 85 A DIR 95 A EXT ...

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... M68HC11K Family MOTOROLA — — — — — — — — — — — ...

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... LSLB Logical Shift Left LSLD Logical Shift Left Double LSR (opr) Logical Shift Right 0 b7 LSRA Logical Shift Right LSRB Logical Shift Right M68HC11K Family MOTOROLA Addressing Instruction Mode Opcode SP INH 31 IX INH 08 IY INH 18 08 EXT IND IND DIR 9D dd ...

Page 60

... M68HC11K Family MOTOROLA C — — — — — — — — — — — — ...

Page 61

... Subtract D – Memory from D SWI Software See Figure 3-2 Interrupt TAB Transfer TAP Transfer Register TBA Transfer TEST TEST (Only in Address Bus Counts Test Modes) M68HC11K Family MOTOROLA Addressing Instruction Mode Opcode A INH IMM 82 A DIR 92 A EXT B2 A IND IND,Y 18 ...

Page 62

... Bit not changed Bit always cleared Bit always set Bit cleared or set, depending on operation Bit can be cleared, cannot become set M68HC11K Family MOTOROLA C — — — — — — — — ...

Page 63

... M68HC11K Family MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Single-Chip Mode Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Special Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Mode Selection Memory Map Control Registers and RAM . . . . . . . . . . . . . . . . . . . . . . . . . 84 ROM or EPROM .87 EEPROM ...

Page 64

... CONFIG Register RAM). 4-1. lists the entire 128-byte register block in ascending order by Operating Modes and On-Chip Memory 4.3 Control Registers 4.4 System 4.6 Memory Map 4.7 EPROM/OTPROM and 4.8 EEPROM and the 4.6.1 Control 4.4 System Initialization. 4.5 Operating M68HC11K Family MOTOROLA ...

Page 65

... Write: See page 142. Reset: Read: Port D Data Direction $0009 Register (DDRD) Write: See page 142. Reset: Figure 4-1. Register and Control Bit Assignments (Sheet 1 of 11) M68HC11K Family MOTOROLA Bit PA7 PA6 PA5 PA4 Undefined after reset DDA7 DDA6 DDA5 ...

Page 66

... Bit 0 PE3 PE2 PD1 PD0 FOC5 OC1M3 OC1D3 Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit Bit 11 Bit 10 Bit 9 Bit 8 Bit 3 Bit 2 Bit 1 Bit 0 Bit 11 Bit 10 Bit 9 Bit 8 Bit 3 Bit 2 Bit 1 Bit 0 Bit 11 Bit 10 Bit 9 Bit 8 = Reserved U = Undefined M68HC11K Family MOTOROLA ...

Page 67

... Register (TOC4H) Reset: See page 197. Timer Output Read: Compare 4 Low Write: $001D Register (TOC4L) Reset: See page 197. Figure 4-1. Register and Control Bit Assignments (Sheet 3 of 11) M68HC11K Family MOTOROLA Bit Bit 7 Bit 6 Bit 5 Bit 4 Undefined after reset Bit 15 Bit 14 Bit 13 ...

Page 68

... Operating Modes and On-Chip Memory Bit 0 Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit OM4 OL4 OM5 OL5 EDG2B EDG2A EDG3B EDG3A I4/O5I IC1I IC2I IC3I I4/O5F IC1F IC2F IC3F ( PR1 PR0 I4/O5 RTR1 RTR0 Bit 3 Bit 2 Bit 1 Bit 0 = Reserved U = Undefined M68HC11K Family MOTOROLA (1) ...

Page 69

... Read: Control/Status Register Write: $0030 (ADCTL) Reset: See page 227. Analog-to-Digital Read: Results Register 1 Write: $0031 (ADR1) Reset: See page 229. Figure 4-1. Register and Control Bit Assignments (Sheet 5 of 11) M68HC11K Family MOTOROLA Bit SPIE SPE DWOM MSTR SPIF WCOL 0 MODF ...

Page 70

... ADPU CSEL IRQE DLY Unimplemented R Operating Modes and On-Chip Memory Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 BPRT3 BPRT2 BPRT1 BPRT0 LSBF SPR2 XDV1 XDV0 (5) (5) CME FCME CR1 CR0 Reserved U = Undefined M68HC11K Family MOTOROLA (5) ...

Page 71

... See pages 235, 243 Reset: Memory Mapping Read: Window Base Register Write: $0057 (2) (MMWBR) Reset: See page 236. 2. Not available on M68HC11KS devices Figure 4-1. Register and Control Bit Assignments (Sheet 7 of 11) M68HC11K Family MOTOROLA Bit Bit 7 Bit 6 Bit 5 Bit LVPI ODD EVEN ...

Page 72

... X1A14 X1A13 X2A15 X2A14 X2A13 GP2SA GP2SB PCSA PCSB GCSPR PCSEN PCSZA PCSZB G1A14 G1A13 G1A12 G1A11 G1SZA G1SZB G1SZC G1SZD G2A14 G2A13 G2A12 G2A11 G2SZA G2SZB G2SZC G2SZD PCKB3 PCKB2 PCKB1 PPOL4 PPOL3 PPOL2 PPOL1 Reserved U = Undefined M68HC11K Family MOTOROLA ...

Page 73

... Timer Period 3 Register Write: $006A (PWPER3) Reset: See page 218. Pulse Width Modulation Read: Timer Period 4 Register Write: $006B (PWPER4) Reset: See page 218. Figure 4-1. Register and Control Bit Assignments (Sheet 9 of 11) M68HC11K Family MOTOROLA Bit Bit 7 Bit 6 Bit 5 Bit TPWSL DISCP ...

Page 74

... Unimplemented R Operating Modes and On-Chip Memory Bit 0 Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit SBR11 SBR10 SBR9 SBR8 SBR3 SBR2 SBR1 SBR0 WAKE ILT RWU SBK RAF Reserved U = Undefined M68HC11K Family MOTOROLA ...

Page 75

... Write: See page 145. Reset: Read: Port G Data Direction $007F Register (DDRG) Write: See page 145. Reset: 1. Not available on M68HC11KS devices Figure 4-1. Register and Control Bit Assignments (Sheet 11 of 11) M68HC11K Family MOTOROLA Bit R7/T7 R6/T6 R5/T5 R4/T4 Undefined after reset ...

Page 76

... Bits [7:6], bit 3 See HPRIO — description — — All, set or clear — All, set or clear — Bits [7:4] See OPT2 — description — All, set or clear See HPRIO — description — All, set or clear See CONFIG — description M68HC11K Family MOTOROLA ...

Page 77

... This includes: • • • M68HC11K Family MOTOROLA Single-chip mode — All port pins available for input/output (I/O); only on-board memory accessible Expanded mode — Access to internal and external memory; 25 I/O pins used for interface Bootstrap mode — A variation of single-chip mode; executes a ...

Page 78

... TxD signal. The bootloader program ends the download after the RAM is full or when the received data line is idle for at least four character times. See Operating Modes and On-Chip Memory Section 11. Memory Expansion Table 4-2) to the SCI Table 4-2. M68HC11K Family MOTOROLA ...

Page 79

... For a detailed description of bootstrap mode, refer to the Motorola application note entitled MC68HC11 Bootstrap Mode, document order number AN1060/D. 4.5.4 Special Test Mode Special test mode, a variation of the expanded mode, is used primarily during Motorola’s internal production testing. However, for those devices ...

Page 80

... Miscellaneous Register (HPRIO Bootloader ROM disabled and not in map 1 = Bootloader ROM enabled and located in map at $BE00–$BFFF Operating Modes and On-Chip Memory Figure 4-2. Control Bits in HPRIO Latched at Reset RBOOT SMOD PSEL3 PSEL2 PSEL1 M68HC11K Family MOTOROLA MDA Bit 0 PSEL0 0 ...

Page 81

... M68HC11K4 Family and M68HC11KS Family memory maps for each of the four modes of operation. Memory locations for on-chip resources are the same for both expanded and single-chip modes. M68HC11K Family MOTOROLA Table 4-1) before clearing SMOD Normal mode operation in effect 1 = Special mode operation in effect ...

Page 82

... BE REMAPPED TO ANY 4-KBYTE BOUNDARY BY THE INIT REGISTER) 640 BYTES EEPROM (CAN BE REMAPPED TO ANY 4-KBYTE BOUNDARY BY THE INIT2 REGISTER) BOOT ROM BE00 (ONLY PRESENT IN SPECIAL BOOT MODE) BFC0 SPECIAL MODES INTERRUPT BFFF VECTORS FFC0 NORMAL MODES INTERRUPT VECTORS FFFF M68HC11K Family MOTOROLA ...

Page 83

... EXPANDED BOOTSTRAP CHIP Note: 1.EPROM can be enabled in special test mode by setting the ROMON bit in the CONFIG register after reset. Figure 4-4. M68HC11KS2 Family Memory Map Table 4-4 Family devices. M68HC11K Family MOTOROLA EXTERNAL EXTERNAL 32K ROM/ EPROM (CAN BE RE-MAPPED TO $0000–$7FFF ...

Page 84

... These four bits determine the position of the register block in memory by specifying the upper hexadecimal digit of the block address. Refer to Technical Data 84 Bit RAM3 RAM2 RAM1 RAM0 Figure 4-5. RAM and I/O Mapping Register (INIT) 4-5. Table 4-6. Operating Modes and On-Chip Memory Bit 0 REG3 REG2 REG1 REG0 M68HC11K Family MOTOROLA ...

Page 85

... RAM[3:0] = REG[3:0]: On the [7]11KS2, RAM address range is $x080–$x47F. 2. RAM[3:0] 3. Default locations out of reset M68HC11K Family MOTOROLA Table 4-5. RAM Mapping RAM[3:0] Address 0000 $0080–$037F 0001 $1080–$137F 0010 $2080–$237F 0011 $3080–$337F 0100 $4080– ...

Page 86

... M68HC11K Family MOTOROLA ...

Page 87

... NOTE: On the M68HC11K devices, the EEPROM can be mapped to where it will contain the vector space. M68HC11K Family MOTOROLA On the [7]11KS2, (EP)ROM mapped to $8000–$FFFF by default, and moved to $0000–$7FFF by clearing the ROMAD bit. Figure 4-6). It can be relocated to any 4-K Figure 4-7) ...

Page 88

... EEPROM disabled 1 = 640-byte EEPROM enabled Operating Modes and On-Chip Memory Bit 0 NOSEC NOCOP ROMON EEON — — — — M68HC11K Family MOTOROLA ...

Page 89

... Reset: NOTE: INIT2 is writable once in normal modes and writable at any time in special modes. EE[3:0] — EEPROM Map Position Bits These four bits determine the most-significant hexadecimal digit in the address range of the EEPROM, as shown in M68HC11K Family MOTOROLA Bit EE3 EE2 EE1 EE0 ...

Page 90

... Programming individual bytes from memory Ensure that the CONFIG register ROMON bit is set. Ensure that the IRQ pin is pulled to a high level. Apply 12 volts to the XIRQ/V PP Operating Modes and On-Chip Memory pin. pin. PP M68HC11K Family MOTOROLA ...

Page 91

... EPROM array. After the MCU receives the last byte to be programmed and returns the corresponding verification data, it terminates the programming operation by initiating a reset. Refer to the Motorola application note entitled MC68HC11 Bootstrap Mode, document order number AN1060/D. 4.7.2 Programming the EPROM from Memory In this method, software programs the EPROM one byte at a time ...

Page 92

... Extra columns selected and user array disabled 0 = User array selected 1 = Extra rows selected and user array is disabled 0 = Programming voltage to EPROM array is disconnected 1 = Programming voltage to EPROM array is connected; ELAT cannot be changed. Operating Modes and On-Chip Memory ) to the EPROM. EPGM can PP M68HC11K Family MOTOROLA ...

Page 93

... EELAT set and PGM cleared. This must be followed by a write to a valid EEPROM location or to the CONFIG address, and then a write to PPROG with both the EELAT and EPGM bits set. Any attempt to set M68HC11K Family MOTOROLA EPROG LDAB #$20 STAB $002B Set ELAT bit to enable EPROM latches ...

Page 94

... This bit is accessible only in test mode. Technical Data 94 Block protect register (BPROT) EEPROM programming control register (PPROG) System configuration options register (OPTION) Bit LVPI ODD EVEN BYTE Unimplemented Operating Modes and On-Chip Memory Bit 0 ROW ERASE EELAT EEPGM M68HC11K Family MOTOROLA ...

Page 95

... ERASE — Erase/Normal Control for EEPROM Bit EELAT — EEPROM Latch Control Bit EEPGM — EEPROM Program Command Bit M68HC11K Family MOTOROLA 0 = Row or bulk erase mode used 1 = Erase only one byte of EEPROM 0 = All 640 bytes of EEPROM erased 1 = Erase only one 16-byte row of EEPROM Table 4-8 ...

Page 96

... EEPROM cannot be bulk or row erased Low-voltage programming inhibit (LVPI) for EEPROM disabled 1 = Low-voltage programming inhibit (LVPI) for EEPROM disabled 0 = Protection disabled for associated block 1 = Protection enabled for associated block Operating Modes and On-Chip Memory Bit 0 BPRT3 BPRT2 BPRT1 BPRT0 Table 4-9 M68HC11K Family MOTOROLA ...

Page 97

... A single byte, a row, or the entire EEPROM in a single procedure can be erased by adjusting the BYTE and ROW bits in PPROG. Once the targeted area has been erased, each byte can be individually written. M68HC11K Family MOTOROLA Table 4-9. EEPROM Block Protect Bit Name Block Protected BPRT0 $xD80– ...

Page 98

... STAA $0,X Store data to EPROM address LDAB #$03 STAB $002B Set EPGM bit with ELAT=1 to enable EEPROM programming voltage JSR DLY10 Delay 10 ms CLR $003B Turn off programming voltage and set to READ mode Operating Modes and On-Chip Memory M68HC11K Family MOTOROLA ...

Page 99

... EEPROM Bulk Erase 4.8.2.3 EEPROM Row Erase 4.8.2.4 EEPROM Byte Erase M68HC11K Family MOTOROLA BULKE LDAB #$06 STAB $003B STAA $0,X LDAB #$07 STAB $002B JSR DLY10 CLR $003B ROWE LDAB #$07 STAB $003B STAA $0,X LDAB #$07 STAB $002B JSR DLY10 CLR $003B ...

Page 100

... Figure 4-12. Block Protect Register (BPROT CONFIG register can be programmed or erased normally CONFIG register cannot be programmed or erased. Erase the CONFIG register. Program the new value to the CONFIG address. Initiate reset. Operating Modes and On-Chip Memory Bit 0 BPRT3 BPRT2 BPRT1 BPRT0 M68HC11K Family MOTOROLA ...

Page 101

... However, on special request, a mask option is selected during fabrication that enables the security mode. The secure mode can be invoked on these parts by clearing NOSEC. Contact a Motorola representative for information on the availability of this feature. The bootstrap program performs this sequence when the security feature is present, enabled, and bootstrap mode is selected: 1 ...

Page 102

... ROMAD 1 CLKX PAREN — 1 — — Figure 4-14. System Configuration Register (CONFIG The XOUT pin is disabled The X clock is driven out on the XOUT pin. Operating Modes and On-Chip Memory Section 2. Pin Bit 0 NOSEC NOCOP ROMON EEON 1 — — — M68HC11K Family MOTOROLA ...

Page 103

... XOUT to stabilize. The phase relationship between XOUT and XTAL cannot be predicted. EXTAL Frequency at XDV[1:0] Divided By EXTAL = 8 MHz M68HC11K Family MOTOROLA Bit (1) LIRDV CWOM STRCH Not available on M68HC11K devices Table 4-10. The divisor is set to 1 out of reset Table 4-10. XOUT Frequencies Frequency at EXTAL = 12 MHz 8 MHz 12 MHz 2 MHz 3 MHz 1 ...

Page 104

... Operating Modes and On-Chip Memory Technical Data 104 Operating Modes and On-Chip Memory M68HC11K Family MOTOROLA ...

Page 105

... M68HC11K Family MOTOROLA Section 5. Resets and Interrupts Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Sources of Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Power-On Reset (POR 107 External Reset (RESET 107 Computer Operating Properly (COP) System . . . . . . . . . . 107 System Configuration Register . . . . . . . . . . . . . . . . . . . 108 System Configuration Options Register . . . . . . . . . . . . . 109 Arm/Reset COP Timer Circuitry Register ...

Page 106

... Computer operating properly (COP) system Clock monitor Table 5-1. Reset Vectors POR or RESET Mode $FFFE and $FFFF $BFFE and $BFFF Resets and Interrupts Table 5-1. Clock Monitor COP Watchdog $FFFC and $FFFD $FFFA and $FFFB $BFFC and $BFFD $BFFA and $BFFB M68HC11K Family MOTOROLA ...

Page 107

... When the COP is enabled, software periodically reinitializes a free-running watchdog timer before it times out and resets the system. Such a system reset indicates that a software error has occurred. M68HC11K Family MOTOROLA generates a POR, which is used only for DD Resets and Interrupts Resets and Interrupts ...

Page 108

... The COPRST register must be written by software to reset the watchdog timer. Figure 5-1). In special test and bootstrap Bit ROMAD 1 CLKX PAREN — 1 — — Figure 5-1. System Configuration Register (CONFIG COP enabled 1 = COP disabled Resets and Interrupts Bit 0 NOSEC NOCOP ROMON EEON 1 — — — M68HC11K Family MOTOROLA ...

Page 109

... EXTAL Freq. 8.0 MHz E Clock Freq. 2.0 MHz Control Bits SPR[2:0] 0/+16.384 16.384 65.536 262.144 1.049 sec M68HC11K Family MOTOROLA Bit ADPU CSEL IRQE and applying a further scaling factor selected Table Table 5-2. COP Timeout EXTAL Frequencies 12.0 MHz 16.0 MHz 3 ...

Page 110

... Because the COP needs a clock to function disabled when the clocks stop. Thus, the clock monitor system can detect clock failures not detected by the COP system. Technical Data 110 Bit Bit 7 Bit 6 Bit 5 Bit Resets and Interrupts Bit 0 Bit 3 Bit 2 Bit 1 Bit M68HC11K Family MOTOROLA ...

Page 111

... Semiconductor wafer processing causes variations of the RC timeout values between individual devices. An E-clock frequency below 10 kHz generates a clock monitor error. An E-clock frequency of 200 kHz or more prevents clock monitor errors. Using the clock monitor function when the E clock is below 200 kHz is not recommended. M68HC11K Family MOTOROLA Figure Bit ADPU ...

Page 112

... Enable LIR push-pull drive 0 = LIR not driven high on MODA/LIR pin 1 = Port C outputs are open drain Port C operates normally Off-chip accesses are selectively extended by one E-clock cycle Normal operation Resets and Interrupts LSBF SPR2 XDV1 Section 6. Parallel Input/Output. M68HC11K Family MOTOROLA Bit 0 XDV0 0 ...

Page 113

... Single-chip Expanded Bootstrap Special test M68HC11K Family MOTOROLA 1 = Data from internal reads is driven out of the external data bus visibility of internal reads on external bus pin is driven low clock is driven out from the chip. Table 5-3 for a summary of the operation immediately Table 5-3 ...

Page 114

... Frequency at XOUT = EXTAL EXTAL = Divided By 8 MHz 1 8 MHz 4 2 MHz 6 1.3 MHz 8 1 MHz Resets and Interrupts Section 8. Serial Peripheral (SPI). Frequency at Frequency at EXTAL = EXTAL = 12 MHz 16 MHz 12 MHz 16 MHz 3 MHz 4 MHz 2 MHz 2.7 MHz 1.5 MHz 2 MHz M68HC11K Family MOTOROLA ...

Page 115

... M68HC11K Family MOTOROLA Central processor unit (CPU) – The stack pointer and other CPU registers are indeterminate immediately after reset, except for three bits in the condition code register (CCR). – The X and I interrupt mask bits are set to mask any interrupt requests, and the S bit in the CCR is set to inhibit the stop mode ...

Page 116

... The send break and receiver wake-up functions are disabled. – The TDRE and TC status bits in the SCI status register are both set, indicating that there is no transmit data in either the transmit data register or the transmit serial shift register. Resets and Interrupts (7.9.1 SCI Baud M68HC11K Family MOTOROLA ...

Page 117

... XIRQ pin. assignments for each source. M68HC11K Family MOTOROLA – The RDRF, IDLE, OR, NF, FE, PF, and RAF receive-related status bits are cleared. Serial peripheral interface (SPI) – The SPI system is disabled by reset. ...

Page 118

... I bit PAII I bit PAOVI I bit TOI I bit I4/O5I I bit OC4I I bit OC3I I bit OC2I I bit OC1I I bit IC3I I bit IC2I I bit IC1I I bit RTII I bit None X bit None None None None None None NOCOP None CME None None M68HC11K Family MOTOROLA ...

Page 119

... The interrupt service routine ends with the return-from-interrupt (RTI) instruction, which tells the CPU to pull the saved registers from the stack in reverse order so that normal program execution can resume. M68HC11K Family MOTOROLA Table 5-6. After the CCR value is stacked, the I bit is Table 5-6. Stacking Order on Entry to Interrupts ...

Page 120

... The illegal opcode service routine can use this stacked address as a pointer to the illegal opcode to correct it. To avoid repeated Technical Data 120 XIRQ pin Illegal opcode trap Software interrupt instruction (SWI) Resets and Interrupts M68HC11K Family MOTOROLA ...

Page 121

... Can be written only once in first 64 cycles out of reset in normal modes or at any time in special modes Figure 5-6. System Configuration Options Register (OPTION) IRQE — Configure IRQ for Edge-Sensitive Operation Bit This bit can be written only once during the first 64 E-clock cycles after reset in normal modes. M68HC11K Family MOTOROLA Figure 5-6). Bit (1) ...

Page 122

... Timer output compare 2 8. Timer output compare 3 9. Timer output compare 4 10. Timer input capture 4/output compare 5 11. Timer overflow 12. Pulse accumulator overflow 13. Pulse accumulator input edge 14. SPI transfer complete 15. SCI system Technical Data 122 Resets and Interrupts M68HC11K Family MOTOROLA ...

Page 123

... Reset and Interrupt Processing This section presents flow diagrams of the reset and interrupt processes. Figure 5-8 detection relates to normal opcode fetches block in shows the resolution of interrupt sources within the SCI subsystem. M68HC11K Family MOTOROLA Figure 5-7). An interrupt that is assigned highest priority is Bit RBOOT ...

Page 124

... Timer output compare 5/input capture Timer overflow Pulse accumulator overflow Pulse accumulator input edge SPI serial transfer complete SCI serial system Reserved (default to IRQ Reserved (default to IRQ Reserved (default to IRQ Reserved (default to IRQ) Resets and Interrupts Interrupt Source Promoted M68HC11K Family MOTOROLA ...

Page 125

... DELAY 4064 E CYCLES LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFE, $FFFF (VECTOR FETCH) Figure 5-8. Processing Flow Out of Reset (Sheet M68HC11K Family MOTOROLA EXTERNAL RESET CLOCK MONITOR FAIL (WITH CME = 1) LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFC, $FFFD (VECTOR FETCH) SET BITS S, I, AND X ...

Page 126

... SWI Y INSTRUCTION? N RTI Y INSTRUCTION? N RESTORE CPU REGISTERS EXECUTE THIS FROM STACK INSTRUCTION 1A Resets and Interrupts STACK CPU REGISTERS STACK CPU REGISTERS ANY N INTERRUPT PENDING? Y SET BIT I IN CCR RESOLVE INTERRUPT PRIORITY AND FETCH VECTOR FOR HIGHEST PENDING SOURCE M68HC11K Family MOTOROLA ...

Page 127

... X BIT IN CCR SET ? NO HIGHEST PRIORITY INTERRUPT ? NO IRQ ? NO RTII = IC1I = IC2I = IC3I = OC1I = Figure 5-9. Interrupt Priority Resolution (Sheet M68HC11K Family MOTOROLA YES YES XIRQ PIN LOW ? NO YES YES YES YES REAL-TIME INTERRUPT ? NO YES YES TIMER IC1F ? NO YES YES TIMER IC2F ? NO YES ...

Page 128

... TOF = 1? $FFDE, $FFDF N Y FLAG FETCH VECTOR PAOVF = 1 $FFDC, $FFDD N Y FLAG FETCH VECTOR PAIF = 1? $FFDA, $FFDB N FLAGS Y FETCH VECTOR SPIF = 1? OR $FFD8, $FFD9 MODF = 1? N FETCH VECTOR $FFD6, $FFD7 FETCH VECTOR $FFF2, $FFF3 Resets and Interrupts 2B END M68HC11K Family MOTOROLA ...

Page 129

... RAM contents. The wait condition suspends processing, reducing power consumption to an intermediate level. The stop condition turns off all on-chip clocks as well and reduces power consumption to an absolute minimum. M68HC11K Family MOTOROLA Y RIE = ...

Page 130

... RAM and register contents are preserved as long are not altered by STOP, so the MCU resumes processing seamlessly after the system is reactivated by an interrupt. However reset is used Technical Data 130 power is maintained. The CPU state and I/O pin levels are static and Resets and Interrupts M68HC11K Family MOTOROLA ...

Page 131

... Address: $0039 Read: Write: Reset: 1. Can be written only once in first 64 cycles out of reset in normal modes or at any time in special modes Figure 5-11. System Configuration Options Register (OPTION) M68HC11K Family MOTOROLA Figure Bit (1) ADPLE DSEL ...

Page 132

... MCU slow down, including the timer, SCI, SPI, and A/ also cleared in hardware when entering stop mode or when reset, including POR, is asserted low When the SM bit is negated, the divider is disconnected and the system runs at normal bus speed. Resets and Interrupts Figure 5-12 Bit M68HC11K Family MOTOROLA ...

Page 133

... EXTAL XTAL OSCILLATOR SM BIT IMMEDIATE CHANGE Figure 5-13. Slow Mode Example for M68HC(7)11KS Devices Only M68HC11K Family MOTOROLA XTAL DIVIDE REQUIRES LOW/HI/LOW ON XTAL — DIVIDE BY 16 RESETS — MUX-OUT LOW CONTROL LOGIC 8 CYCLES — DIVIDE BY 16 HIGH 8 CYCLES — DIVIDE BY 16 LOW ...

Page 134

... Resets and Interrupts Technical Data 134 Resets and Interrupts M68HC11K Family MOTOROLA ...

Page 135

... Contents 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 M68HC11K Family MOTOROLA Section 6. Parallel Input/Output Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Port 138 Port 139 Port 140 Port 142 Port 143 Port 144 Port 145 Port 146 Internal Pullup Resistors 147 Parallel Input/Output ...

Page 136

... Parallel Input/Output 2.11 Port Signals and Shared Functions Timer High-order address Data bus SCI and SPI A/D converter Low-order address Memory expansion Chip selects and PWM M68HC11K Family MOTOROLA ...

Page 137

... U in the register descriptions that follow. NOTE: Throughout this manual, the registers are discussed by function. In the event that not all bits in a register are referenced, the bits that are not discussed are shaded. M68HC11K Family MOTOROLA Resistors. Parallel Input/Output Parallel Input/Output Introduction 6.11 Internal ...

Page 138

... OC1 OC1 OC1 OC1 Figure 6-1. Port A Data Register (PORTA) Bit DDA7 DDA6 DDA5 DDA4 Input 1 = Output Parallel Input/Output System Bit 0 PA3 PA2 PA1 PA0 IC4/OC5 IC1 IC2 IC3 OC1 — — — Bit 0 DDA3 DDA2 DDA1 DDA0 M68HC11K Family MOTOROLA ...

Page 139

... ADDR[15:8] for external memory devices. Address: $0004 Read: Write: Reset: Single-Chip/Boot: Expanded/Test: ADDR15 Address: $0002 Read: Write: Reset: DDB[7:0] — Data Direction for Port B Bits M68HC11K Family MOTOROLA Bit PB7 PB6 PB5 PB7I PB6 PB5 ADDR14 ADDR13 Figure 6-3. Port B Data Register (PORTB) ...

Page 140

... Bit PC7 PC6 PC5 PC4 Undefined after reset PC7I PC6 PC5 PC4 DATA7 DATA6 DATA5 DATA4 Figure 6-5. Port C Data Register (PORTC) Parallel Input/Output Bit 0 PC3 PC2 PC1 PC0 PC3 PC2 PC1 PC0 DATA3 DATA2 DATA1 DATA0 M68HC11K Family MOTOROLA ...

Page 141

... In expanded modes, setting this bit drives MCU’s internal data bus on port C. In single-chip modes, setting this bit inhibits the E clock driver, and the E pin is pulled low NOTE: IRVNE can be written only once after reset. The default value of IRVNE after reset is low. M68HC11K Family MOTOROLA Bit DDC7 DDC6 DDC5 0 ...

Page 142

... PD5 PD4 — — SS SCK U = Undefined Figure 6-8. Port D Data Register (PORTD) Bit DDD5 DDD4 Input 1 = Output Parallel Input/Output (SCI)) and Section 8. Serial Peripheral PD3 PD2 PD1 MOSI MISO TxD DDD3 DDD2 DDD1 M68HC11K Family MOTOROLA Bit 0 PD0 U RxD Bit 0 DDD0 0 ...

Page 143

... Converter). NOTE: PORT E should not be read during the sample portion of an A/D conversion. Address: $000A Read: Write: Reset: Alternate Pin Function: M68HC11K Family MOTOROLA Section 10. Analog-to-Digital (A/D) Bit PE7 PE6 PE5 PE4 Undefined after reset AN7 ...

Page 144

... AN5 AN4 Figure 6-11. Port F Data Register (PORTF) Bit DDF7 DDF6 DDF5 DDF4 Input 1 = Output Parallel Input/Output 6.11 Internal Pullup Bit 0 PF3 PF2 PF1 PF0 PF3 PF2 PF1 PF0 AN3 AN2 AN1 AN0 Bit 0 DDF3 DDF2 DDF1 DDF0 M68HC11K Family MOTOROLA ...

Page 145

... Internal Pullup Address: $007E Read: Write: Reset: Alternate Pin Function: 1. Not available on KS devices Address: $007F Read: Write: Reset: 1. Not available on KS devices DDG[7:0] — Data Direction for Port G Bits M68HC11K Family MOTOROLA Resistors). Bit (1) (1) PG7 PG6 PG5 R/W — ...

Page 146

... PH5 PH4 CSPG2 CSPG1 CSIO Figure 6-15. Port H Data Register (PORTH) Bit (1) (1) (1) DDH7 DDH6 DDH5 DDH4 Input 1 = Output Parallel Input/Output 9.9 Pulse-Width Modulator (1) PH3 PH2 PH1 PW4 PS3 PS2 (1) DDH3 DDH2 DDH1 M68HC11K Family MOTOROLA Bit 0 PH0 0 PS1 Bit 0 DDH0 0 ...

Page 147

... B are address outputs. Address: $003F Read: Write: Reset: Figure 6-18. System Configuration Register (CONFIG) NOTE: CONFIG is writable once in normal modes and writable at any time in special modes. PAREN — Pullup Assignment Register Enable Bit M68HC11K Family MOTOROLA Figure 6-17 Bit Port x pin on-chip pullup devices disabled ...

Page 148

... Parallel Input/Output Technical Data 148 Parallel Input/Output M68HC11K Family MOTOROLA ...

Page 149

... Several baud rates are available. The SCI transmitter and receiver are independent, but they use the same data format and baud rate. M68HC11K Family MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Wakeup Feature ...

Page 150

... After the last break character is sent, the line goes high for at least one bit time. Serial Communications Interface (SCI) NEXT START STOP BIT7 BIT BIT PARITY OR DATA NEXT BIT START BIT 7 STOP BIT 8 BIT BIT M68HC11K Family MOTOROLA ...

Page 151

... TDRE flags are set at the completion of this last character, even though TE has been disabled. Only an MCU reset can abort transmission in midcharacter. M68HC11K Family MOTOROLA Figure 5-10. Interrupt Priority Resolution Within SCI for a flow diagram of SCI interrupts. Serial Communications Interface (SCI) Serial Communications Interface (SCI) ...

Page 152

... SCI transmitter. WRITE ONLY FORCE PIN DIRECTION (OUT) TRANSMITTER TE CONTROL LOGIC SCSR1 SCI STATUS 1 TDRE TIE TC TCIE SCCR2 SCI CONTROL 2 Serial Communications Interface (SCI) (1) DDD1 PIN BUFFER PD1 AND CONTROL TxD INTERNAL DATA BUS M68HC11K Family MOTOROLA ...

Page 153

... These flags can be read (polled) at any time by software. Each bit except RAF is cleared by reading SCSR1 and SCDR sequentially. • • M68HC11K Family MOTOROLA Table 7-1. SCI Receiver Flags Name Receive data Character transferred from shift register register full ...

Page 154

... The receiver active flag (RAF read-only bit that is set during data reception and cleared when the line goes idle. This is the only flag cleared by hardware block diagram of the SCI receiver. Serial Communications Interface (SCI) M68HC11K Family MOTOROLA ...

Page 155

... RxD DISABLE DRIVER SCSR2 SCI STATUS 2 SCCR1 SCI CONTROL 1 SCI Rx SCI INTERRUPT REQUESTS REQUEST Note 1. Data direction register for port D Figure 7-3. SCI Receiver Block Diagram M68HC11K Family MOTOROLA 16 DATA H RECOVERY PARITY DETECT WAKEUP LOGIC SCSR1 SCI STATUS 1 RDRF RIE IDLE ...

Page 156

... Unlike the idle line method, address mark wakeup allows idle periods within messages and does not require idle time between messages. However, message processing is less efficient because the start bit of each character must be evaluated. Serial Communications Interface (SCI) M68HC11K Family MOTOROLA ...

Page 157

... Writing to the SCI baud rate register (SCBDH/L) selects the prescaler value. See EXTAL 13-BIT COUNTER 13-BIT COMPARE SCBDH/L SCI BAUD RATE CONTROL Figure 7-4. SCI Baud Generator Circuit Diagram M68HC11K Family MOTOROLA INTERNAL PHASE 2 CLOCK RESET SYNCH 2 Serial Communications Interface (SCI) Serial Communications Interface (SCI) ...

Page 158

... Normally, this register is written once Bit BTST BSPL 0 SBR12 Undefined Bit SBR7 SBR6 SBR5 SBR4 Undefined Figure 7-6. SCI Baud Rate Control Register Low (SCBDL) Serial Communications Interface (SCI) Figure 7-4 to generate SBR11 SBR10 SBR9 SBR3 SBR2 SBR1 M68HC11K Family MOTOROLA Bit 0 SBR8 U Bit 0 SBR0 U ...

Page 159

... M68HC11K Family MOTOROLA SCI baud rate control register value = (EXTAL/32)/target baud rate Table 7-2. SCI+ Baud Rates EXTAL Frequencies 12.0 MHz 16.0 MHz 3.0 MHz 4.0 MHz SCI Baud Rate Control Register Values ...

Page 160

... Wake up by idle line recognition 1 = Wake up by address mark (most significant data bit set Short (SCI counts consecutive 1s after start bit Long (SCI counts one only after stop bit.) Serial Communications Interface (SCI Bit 0 WAKE ILT for a description M68HC11K Family MOTOROLA ...

Page 161

... TCIE — Transmit Complete Interrupt Enable Bit RIE — Receiver Interrupt Enable Bit ILIE — Idle Line Interrupt Enable Bit M68HC11K Family MOTOROLA 0 = Parity disabled 1 = Parity enabled 0 = Parity even (even number of 1s causes parity bit odd number of 1s causes parity bit ...

Page 162

... Receiver disabled 1 = Receiver enabled 0 = Normal SCI receiver operation 1 = Wakeup is enabled and receiver interrupts are inhibited Break generator off 1 = Break codes generated as long as SBK = 1 Bit TDRE TC RDRF IDLE Figure 7-9. SCI Status Register 1 (SCSR1) Serial Communications Interface (SCI Bit M68HC11K Family MOTOROLA ...

Page 163

... NF — Noise Error Flag NF is set after the last bit in a frame is received if the samples in the receiver’s data recovery circuit are not unanimous for any of the bits, including start and stop bits. M68HC11K Family MOTOROLA 0 = SCDR is full SCDR is empty Transmitter busy 1 = Transmitter idle ...

Page 164

... RAF is a read-only bit. Technical Data 164 0 = Stop bit detected 1 = Logic 0 detected at the end of a character 0 = Parity disabled 1 = Parity enabled Bit Unimplemented Figure 7-10. SCI Status Register 2 (SCSR2 Receiver is inactive character is being received. Serial Communications Interface (SCI Bit 0 RAF M68HC11K Family MOTOROLA ...

Page 165

... Reset: Address $0077 Read: Write: Reset: R8 and T8 — Receiver Bit 8 and Transmitter Bit 8 Ninth data bit is received or transmitted when the system is configured for 8-bit data using mark address wakeup. R/T[7:0] — Receiver/Transmitter Bits [7:0] M68HC11K Family MOTOROLA Bit Undefined after reset ...

Page 166

... Serial Communications Interface (SCI) Technical Data 166 Serial Communications Interface (SCI) M68HC11K Family MOTOROLA ...

Page 167

... Synchronous communication requires a clock and, in the M68HC11 series, a slave-select signal, but provides substantially faster communication than the asynchronous SCI, which does not require this M68HC11K Family MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 SPI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 SPI Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Master In Slave Out (MISO 170 Master Out Slave In (MOSI) ...

Page 168

... After the last bit of a character is shifted out, the SPI transfer complete flag (SPIF) of the SPSR is set. This will also generate an interrupt if the SPIE (SPI interrupt enable) bit in the SPCR is set. Technical Data 168 Serial Peripheral Interface (SPI) M68HC11K Family MOTOROLA ...

Page 169

... INTERNAL MCU CLOCK DIVIDER 2 ÷ SPI CLOCK (MASTER) SELECT SPI CONTROL SPI STATUS REGISTER SPI INTERRUPT REQUEST M68HC11K Family MOTOROLA shows the SPI block diagram. MSB LSB 8/16-BIT SHIFT REGISTER READ DATA BUFFER CLOCK CLOCK LOGIC MSTR SPE 8 SPI CONTROL REGISTER 8 ...

Page 170

... The SPI clock rate select bits in the master device determine the SCK clock rate. These bits are SPR[1:0] in the serial peripheral control register (SPCR) and SPR2 in the system configuration options 2 register (OPT2). These bits have no effect in a slave device. Technical Data 170 Serial Peripheral Interface (SPI) M68HC11K Family MOTOROLA ...

Page 171

... SPI logic can detect write collisions in both master and slave devices. SCK CYCLE # FOR REFERENCE SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE INPUT (CPHA = 0) DATA OUT MSB SAMPLE INPUT (CPHA = 1) DATA OUT SS (TO SLAVE) M68HC11K Family MOTOROLA 8.5.1 Mode Fault Error). 8- MSB 6 ...

Page 172

... Technical Data 172 if CPHA = 1 at all times mode fault error can occur when multiple devices attempt to act in master mode simultaneously. A write collision error results from an attempt to write data to the SPDR while a transmission is in progress. Serial Peripheral Interface (SPI) M68HC11K Family MOTOROLA ...

Page 173

... The three SPI registers provide control, status, and data storage functions respectively: • • • M68HC11K Family MOTOROLA Serial peripheral control register (SPCR) Serial peripheral status register (SPSR) Serial peripheral data register (SPDR) Serial Peripheral Interface (SPI) Serial Peripheral Interface (SPI) ...

Page 174

... SPI interrupt is enabled each time the SPIF or MODF status flag in SPSR is set SPI off 1 = SPI on — PD[5:2] function as SPI signals 0 = Normal CMOS outputs 1 = Open-drain outputs 0 = Slave mode 1 = Master mode Serial Peripheral Interface (SPI Bit 0 CPOL CPHA SPR1 SPR2 for a discussion M68HC11K Family MOTOROLA ...

Page 175

... M68HC11K Family MOTOROLA Table 8-1. SPI+ Baud Rates EXTAL Frequencies 12.0 MHz 16.0 MHz 20.0 MHz 3.0 MHz 4.0 MHz 5.0 MHz SPI Baud Rate 1.5 MHz 2.0 MHz 2 ...

Page 176

... To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR. Technical Data 176 Bit SPIF WCOL 0 MODF Figure 8-4. Serial Peripheral Status Register (SPSR write collision 1 = Write collision mode fault 1 = Mode fault Serial Peripheral Interface (SPI Bit M68HC11K Family MOTOROLA ...

Page 177

... Address: $002A Read: Write: Reset: A write to SPDR goes directly to the transmission shift register. A read of the SPDR retrieves data from the read data buffer. M68HC11K Family MOTOROLA Bit Bit 7 Bit 6 Bit 5 Bit 4 ...

Page 178

... Technical Data 178 Bit DDD5 DDD4 Figure 8-6. Port D Data Direction Register (DDRD PD5 is an error-detect input to the SPI PD5 is configured as a general-purpose output line. Serial Peripheral Interface (SPI Bit 0 DDD3 DDD2 DDD1 DDD0 M68HC11K Family MOTOROLA ...

Page 179

... MSB first). LSBF does not affect bit positions in the data register; reads and writes always have MSB in bit 7. SPR2 — SPI Clock Rate Select Bit SPR2 adds a divide-by-4 prescaler to the SPI clock chain. With the two bits in the SPCR, this specifies the SPI clock rate. See M68HC11K Family MOTOROLA Bit (1) ...

Page 180

... Serial Peripheral Interface (SPI) Technical Data 180 Serial Peripheral Interface (SPI) M68HC11K Family MOTOROLA ...

Page 181

... M68HC11K Family MOTOROLA Section 9. Timing System Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Timer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Input Capture and Output Compare Overview . . . . . . . . . . . . 185 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Timer Interrupt Flag 2 Register . . . . . . . . . . . . . . . . . . . . . 189 Timer Interrupt Mask 2 Register 189 Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . . 190 Pulse Accumulator Control Register ...

Page 182

... Pulse-Width Modulation Timer Enable Register . . . . . . 216 Pulse-Width Modulation Timer Counters1 to 4 Registers . . . . . . . . . . . . . . . . . . . . . 217 Pulse-Width Modulation Timer Periods Registers . . . . . . . . . . . . . . . . . . . . . . 218 Pulse-Width Modulation Timer Duty Cycle Registers . . . . . . . . . . . . . . . . . . .219 Input capture/output compare (IC/OC) Real-time interrupt (RTI) Pulse accumulator (PA) Pulse width modulation (PWM) Timing System M68HC11K Family MOTOROLA ...

Page 183

... PH2 bus clock, are derived from the oscillator output divided by four. EXTAL OSCILLATOR 4 PRESCALER ( 16, 32, 64, 128) SPR[2:0] PRESCALER ( 16) PR[1:0] TCNT IC/OC M68HC11K Family MOTOROLA Figure 9-1 shows, the primary system clocks, including the E clock XDV[1:0 5......8191) SBR[12:0] POSTSCALER E 2 POSTSCALER TOF ...

Page 184

... Timing System 8.6.1 Serial Peripheral Control 2. shows main timer 20.0 MHz Other EXTAL 5.0 MHz EXTAL/4 200 ns 1/E 1 Count Timer Overflow 1 E 167 ns 16 10.923 667 ns 18 43.961 1.333 s 19 87.381 2.667 s 20 174. M68HC11K Family MOTOROLA ...

Page 185

... All timer functions, including the timer overflow and RTI, have their own interrupt controls and separate interrupt vectors. M68HC11K Family MOTOROLA (RTI). The clock driving this function is also derived from the (5.3.3 Computer Operating Properly (COP) Three input capture channels ...

Page 186

... The PA7 pin can be used as a GPIO pin input to the pulse accumulator OC1 output pin. Timer counter register (TCNT) Timer interrupt flag 2 (TFLG2) Timer interrupt mask 2 (TMSK2) Data direction register A (DDRA) Pulse accumulator control register (PACTL) Timing System M68HC11K Family MOTOROLA ...

Page 187

... LATCH CLK CLK 16-BIT LATCH TIC1 (HI) TIC1 (LO) CLK 16-BIT LATCH TIC2 (HI) TIC2 (LO) CLK 16-BIT LATCH TIC3 (HI) TIC3 (LO) Figure 9-2. Capture/Compare Block Diagram M68HC11K Family MOTOROLA TCNT (HI) TCNT (LO) 16-BIT FREE RUNNING COUNTER OC1F FOC1 OC2F FOC2 OC3F FOC3 OC4F FOC4 OC5 I4/O5F ...

Page 188

... TCNT can be read and written in special modes. Technical Data 188 Bit Bit 15 Bit 14 Bit 13 Bit Bit 7 Bit 6 Bit 5 Bit Unimplemented Figure 9-3. Timer Counter Register (TCNT) Timing System Bit 0 Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit M68HC11K Family MOTOROLA ...

Page 189

... Set when TCNT changes from $FFFF to $0000. 9.4.3 Timer Interrupt Mask 2 Register Address: $0024 Read: Write: Reset: Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. TOI — Timer Overflow Interrupt Enable Bit M68HC11K Family MOTOROLA Bit TOF RTIF PAOVF Figure 9-4 ...

Page 190

... Table 9-1 for specific timing values. Table 9-2. Timer Prescale PR[1: Bit DDA7 DDA6 DDA5 DDA4 Figure 9-6. Port A Data Direction Register (DDRA PA3 configured as an input 1 = PA3 configured as an output Timing System Prescaler Bit 0 DDA3 DDA2 DDA1 DDA0 M68HC11K Family MOTOROLA ...

Page 191

... Because these delays offset each other when the time between two edges is measured, they can be ignored. There is a similar delay for output compare between the actual compare point and when the output pin changes state. M68HC11K Family MOTOROLA Bit PAEN ...

Page 192

... Bit 4 Unaffected by reset Figure 9-8. Timer Input Capture Registers (TIC1–TIC3) Timing System Bit 0 Bit 11 Bit 10 Bit 9 Bit 8 Bit 3 Bit 2 Bit 1 Bit 0 Bit 11 Bit 10 Bit 9 Bit 8 Bit 3 Bit 2 Bit 1 Bit 0 Bit 11 Bit 10 Bit 9 Bit 8 Bit 3 Bit 2 Bit 1 Bit 0 M68HC11K Family MOTOROLA ...

Page 193

... If a new input capture occurs immediately after a high-order byte read, transfer is delayed for an additional cycle, but the new value is not lost. To assure coherency between the two bytes, use a double-byte read instruction such as LDD. M68HC11K Family MOTOROLA Bit ...

Page 194

... Technical Data 194 Bit OC1F OC2F OC3F OC4F Figure 9-10. Timer Interrupt Flag 1 Register (TFLG1) Bit OC1I OC2I OC3I OC4I Figure 9-11. Timer Interrupt Mask 1 Register (TMSK1) Timing System Bit 0 I4/O5F IC1F IC2F IC3F Bit 0 I4/O5I IC1I IC2I IC3I M68HC11K Family MOTOROLA ...

Page 195

... Each EDGx bit pair is cleared (IC function disabled) by reset and must be encoded according to the values in corresponding input capture edge detector circuit. IC4 functions only if the I4/O5 bit in the PACTL register is set. M68HC11K Family MOTOROLA Bit EDG4B EDG4A ...

Page 196

... Pulse-Width Modulator Write a value to the output compare register that represents the time the leading edge of the pulse is to occur. Use OC1D to select either a high or low output, depending on the polarity of the pulse being produced. Timing System (PWM)), the M68HC11K Family MOTOROLA ...

Page 197

... Address: $0019 — TOC2 (Low) Read: Write: Reset: M68HC11K Family MOTOROLA After a match occurs, change the appropriate OC1D bit to the opposite polarity, then add a value representing the width of the pulse to the original value and write it to the output compare register. Bit 7 ...

Page 198

... Bit 5 Bit Bit 15 Bit 14 Bit 13 Bit Bit 7 Bit 6 Bit 5 Bit Figure 9-13. Timer Output Compare Registers (TOC1–TOC4) (Continued) Timing System Bit 0 Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit M68HC11K Family MOTOROLA ...

Page 199

... Clear each flag by writing the corresponding bit position. OCxF — Output Compare x Flag Set each time the counter matches output compare x value. I4/O5F — Input Capture 4/Output Compare 5 Flag Set each time the counter matches output compare 5 value if OC5 is enabled. M68HC11K Family MOTOROLA Bit Bit 15 Bit 14 Bit 13 ...

Page 200

... OC2I OC3I OC4I Figure 9-16. Timer Interrupt Mask 1 Register (TMSK1) Bit OM2 OL2 OM3 OL3 Figure 9-17. Timer Control Register 1 (TCTL1) Timing System Bit 0 I4/O5I IC1I IC2I IC3I Bit 0 OM4 OL4 OM5 OL5 Table 9-4 to specify the action M68HC11K Family MOTOROLA 0 0 ...

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