MPC9773 Motorola, MPC9773 Datasheet

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MPC9773

Manufacturer Part Number
MPC9773
Description
3.3V 1:12 LVCMOS PLL Clock Generator
Manufacturer
Motorola
Datasheet

Specifications of MPC9773

Case
QFP

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3.3V 1:12 LVCMOS PLL Clock
Generator
targeted for high performance low-skew clock distribution in mid-range to
high-performance networking, computing and telecom applications. With
output frequencies up to 240 MHz and output skews less than 250 ps the
device meets the needs of the most demanding clock applications.
Features
Functional Description
MPC9773 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The
reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match
the VCO frequency range. The MPC9773 features an extensive level of frequency programmability between the 12 outputs as
well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3.
feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference
versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In
addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a
non–binary factor. The MPC9773 also supports the 180 phase shift of one of its output banks with respect to the other output
banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation
of system baseline timing signals.
LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass
configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers
bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics
do not apply.
MPC9773. The MPC9773 has an internal power–on reset.
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
lines. For series terminated transmission lines, each of the MPC9773 outputs can drive one or two traces giving the devices an
effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package.
1:12 PLL based low-voltage clock generator
3.3V power supply
Internal power–on reset
Generates clock signals up to 240 MHz
Maximum output skew of 250 ps
Differential PECL reference clock input
Two LVCMOS PLL reference clock inputs
External PLL feedback supports zero-delay capability
Various feedback and output dividers (see application section)
Supports up to three individual generated output clock frequencies
Synchronous output clock stop circuitry for each individual output for
power down support
Drives up to 24 clock lines
Ambient temperature range 0 C to +70 C
Pin and function compatible to the MPC973
The MPC9773 is a 3.3V compatible, 1:12 PLL based clock generator
The MPC9773 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the
The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative
The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the
The MPC9773 is fully 3.3V compatible and requires no external loop filter components. All inputs (except PCLK) accept
Motorola, Inc. 2003
Freescale Semiconductor, Inc.
For More Information On This Product,
1
Go to: www.freescale.com
PLL CLOCK GENERATOR
3.3V 1:12 LVCMOS
52 LEAD LQFP PACKAGE
MPC9773
CASE 848D
FA SUFFIX
Order Number: MPC9773/D
W
Rev 3, 02/2003
transmission

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MPC9773 Summary of contents

Page 1

... The MPC9773 also supports the 180 phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals ...

Page 2

... STOP_DATA CLOCK STOP STOP_CLK MR/OE FSEL_B1 40 FSEL_B0 41 FSEL_A1 42 FSEL_A0 43 QA3 44 VCC 45 QA2 46 GND 47 QA1 48 VCC 49 QA0 50 GND 51 VCO_SEL 52 Figure 2. MPC9773 52–Lead Package Pinout (Top View) For More Information On This Product, MOTOROLA VCO PLL 12, 16, 20 Sync Pulse Figure 1. MPC9773 Logic Diagram MPC9773 ...

Page 3

... Selects VCO 2. The VCO frequency is scaled by a factor of 2 (low VCO frequency range). PLL_EN 1 Test mode with the PLL bypassed. The reference clock is substituted for the internal VCO output. MPC9773 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. INV_CLK 1 ...

Page 4

... Freescale Semiconductor, Inc. MPC9773 Table 3. Output Divider Bank VCO_SEL FSEL_A1 FSEL_A0 Table 4. Output Divider Bank VCO_SEL FSEL_B1 FSEL_B0 Table 6. Output Divider PLL Feedback (M) VCO_SEL FSEL_FB2 For More Information On This Product, MOTOROLA Table 5. Output Divider Bank QA[0:3] VCO_SEL FSEL_C1 VCO 8 0 VCO 12 ...

Page 5

... V CMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V CMR range and the input swing lies within the V PP (DC) specification. b. The MPC9773 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage Alternatively, the device drives up to two 50 series terminated transmission lines. c. ...

Page 6

... Freescale Semiconductor, Inc. MPC9773 Table 10. AC CHARACTERISTICS ( 3.3V Symbol Characteristics f REF Input reference frequency Input reference frequency in PLL bypass mode VCO frequency range c f VCO f MAX Output Frequency f STOP_CLK Serial interface clock frequency V PP Peak-to-peak input voltage V CMR d Common Mode Range ...

Page 7

... Calculation of reference duty cycle limits: DC REF,MIN = t PW,MIN f REF 100% and DC REF,MAX = 100 REF, MIN . e The MPC9773 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically PW,MIN , DC and f MAX can only be guaranteed are within the specified range. f CCLKx or PCLK to FB_IN. Static phase offset depends on the reference frequency [ Excluding QSYNC output ...

Page 8

... Freescale Semiconductor, Inc. MPC9773 MPC9773 Configurations Configuring the MPC9773 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: f OUT = f REF REF VCO_SEL PLL M where f REF is the reference frequency of the selected input clock source (CCLKO, CCLK1 or PCLK the PLL feedback divider and output divider ...

Page 9

... NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the free–running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the MPC9773 can sample each STOP_DATA bit with the rising edge of the free–running STOP_CLK signal. (see Figure 5. ) ...

Page 10

... QSYNC. In configurations with the output frequency relationships are not integer multiples of each other QSYNC provides a signal for system synchronization purposes. The MPC9773 monitors the relationship between the A bank and the B bank of outputs. The QSYNC output is asserted (logic low) one period in duration and one period prior to the ...

Page 11

... The simple but effective form of isolation is a power supply filter on the V CCA_PLL pin for the MPC9773. Figure 7. illustrates a typical power supply filter scheme. The MPC9773 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range ...

Page 12

... This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9773 clock driver. For the series terminated case however there current draw, thus the outputs 12 Go to: www.freescale.com FB= 6 FB= 24 ...

Page 13

... This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9773. The output waveform in Figure 13. “Single versus Dual Line Termination Waveforms” shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver ...

Page 14

... Freescale Semiconductor, Inc. MPC9773 Pulse Generator Figure 15. CCLK MPC9773 AC test reference Differential Pulse Generator Figure 16. PCLK MPC9773 AC test reference For More Information On This Product, MOTOROLA MPC9773 DUT MPC9773 DUT to: www.freescale.com TIMING SOLUTIONS ...

Page 15

... GND FB_IN The deviation for a controlled edge with respect mean in a random sample of cycles T 0 The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles V CC =3.3V 2.4 0. to: www.freescale.com MPC9773 GND GND offset) test reference T JIT – ...

Page 16

... Freescale Semiconductor, Inc. MPC9773 4X 0.20 (0.008) H L– VIEW Y 3X –L– –N– –H– –T– q SEATING 4X PLANE 0.05 (0.002 VIEW AA Z For More Information On This Product, MOTOROLA OUTLINE DIMENSIONS FA SUFFIX 52 LEAD LQFP PACKAGE CASE 848D-03 ISSUE TIPS 0.20 (0.008) T L–M ...

Page 17

... Freescale Semiconductor, Inc. For More Information On This Product, TIMING SOLUTIONS NOTES 17 Go to: www.freescale.com MPC9773 MOTOROLA ...

Page 18

... Freescale Semiconductor, Inc. MPC9773 For More Information On This Product, MOTOROLA NOTES 18 Go to: www.freescale.com TIMING SOLUTIONS ...

Page 19

... Freescale Semiconductor, Inc. For More Information On This Product, TIMING SOLUTIONS NOTES 19 Go to: www.freescale.com MPC9773 MOTOROLA ...

Page 20

... Minami–Azabu, Minato–ku, Tokyo 106–8573 Japan 81–3–3440–3569 For More Information On This Product, MOTOROLA ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334 HOME PAGE: http://motorola.com/semiconductors 20 Go to: www.freescale.com MPC9773/D TIMING SOLUTIONS ...

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