IDT72V821 Integrated Device Technology, Inc., IDT72V821 Datasheet

IDT72V821

Manufacturer Part Number

IDT72V821

Description

3.3 VOLT DUAL CMOS SyncFIFO?

Manufacturer

Integrated Device Technology, Inc.

Datasheet

1.IDT72V821.pdf (16 pages)

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dual synchronous (clocked) FIFOs. The device is functionally equivalent to

two IDT72V201/72V211/72V221/72V231/72V241/72V251 FIFOs in a single

package with all associated control, data, and flag lines assigned to separate

pins.

The IDT logo is a registered trademark and the SyncFIFO is a trademark of Integrated Device Technology, Inc.

The IDT72V801 is equivalent to two IDT72V201 256 x 9 FIFOs

The IDT72V811 is equivalent to two IDT72V211 512 x 9 FIFOs

The IDT72V821 is equivalent to two IDT72V221 1,024 x 9 FIFOs

The IDT72V831 is equivalent to two IDT72V231 2,048 x 9 FIFOs

The IDT72V841 is equivalent to two IDT72V241 4,096 x 9 FIFOs

The IDT72V851 is equivalent to two IDT72V251 8,192 x 9 FIFOs

Offers optimal combination of large capacity, high speed,

design flexibility and small footprint

Ideal for prioritization, bidirectional, and width expansion

applications

10 ns read/write cycle time

5V input tolerant

Separate control lines and data lines for each FIFO

Separate Empty, Full, programmable Almost-Empty and

Almost-Full flags for each FIFO

Enable puts output data lines in high-impedance state

Space-saving 64-pin plastic Thin Quad Flat Pack (TQFP/

STQFP)

Industrial temperature range (–40 C to +85 C) is available

2001 Integrated Device Technology, Inc.

The IDT72V801/72V811/72V821/72V831/72V841/72V851/72V851 are

WRITE CONTROL

WRITE POINTER

WCLKA

RESET LOGIC

LOGIC

WENA1

RSA

WENA2

OEA

OUTPUT REGISTER

1,024 x 9, 2,048 x 9,

4,096 x 9, 8,192 x 9

INPUT REGISTER

256 x 9, 512 x 9,

RAM ARRAY

- DA

- QA

3.3 VOLT DUAL CMOS SyncFIFO™

DUAL 256 X 9, DUAL 512 X 9,

DUAL 1,024 X 9, DUAL 2,048 X 9,

DUAL 4,096 X 9 , DUAL 8,192 X 9

OFFSET REGISTER

READ CONTROL

READ POINTER

RCLKA

RENA1

LOGIC

FLAG

RENA2

LDA

EFA

PAEA

PAFA

FFA

IDT72V801/72V811/72V821/72V831/72V841/72V851 has a 9-bit input data

port (DA0 - DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8,

QB0 - QB8). Each input port is controlled by a free-running clock (WCLKA,

WCLKB), and two Write Enable pins (WENA1, WENA2, WENB1, WENB2).

Data is written into each of the two arrays on every rising clock edge of the Write

Clock (WCLKA, WCLKB) when the appropriate Write Enable pins are

asserted.

(RCLKA, RCLKB) and two Read Enable pins (RENA1, RENA2, RENB1,

RENB2). The Read Clock can be tied to the Write Clock for single clock operation

or the two clocks can run asynchronous of one another for dual clock operation.

An Output Enable pin (OEA, OEB) is provided on the read port of each FIFO

for three-state output control.

FFB). Two programmable flags, Almost-Empty (PAEA, PAEB) and Almost-Full

(PAFA, PAFB), are provided for each FIFO bank to improve memory utilization.

If not programmed, the programmable flags default to Empty+7 for PAEA and

PAEB, and Full-7 for PAFA and PAFB.

lends itself to many flexible configurations such as:

technology.

WRITE CONTROL

WCLKB

WRITE POINTER

• 2-level priority data buffering

• Bidirectional operation

• Width expansion

• Depth expansion

RESET LOGIC

Each of the two FIFOs (designated FIFO A and FIFO B) contained in the

The output port of each FIFO bank is controlled by its associated clock pin

Each of the two FIFOs has two fixed flags, Empty (EFA, EFB) and Full (FFA,

The IDT72V801/72V811/72V821/72V831/72V841/72V851 architecture

This FIFO is fabricated using IDT's high-performance submicron CMOS

LOGIC

WENB1

RSB

WENB2

OEB

OUTPUT REGISTER

1,024 x 9, 2,048 x 9,

INPUT REGISTER

4,096 x 9, 8,192 x 9

256 x 9, 512 x 9,

RAM ARRAY

- DB

- QB

OFFSET REGISTER

READ CONTROL

READ POINTER

RCLKB

LOGIC

RENB1

FLAG

RENB2

IDT72V801

IDT72V811

IDT72V821

IDT72V831

IDT72V841

IDT72V851

LDB

4093 drw 01

DSC-4093/1

PAEB

PAFB

EFB

FFB

Related parts for IDT72V821

IDT72V821 Summary of contents

Page 1

... The IDT72V801 is equivalent to two IDT72V201 256 x 9 FIFOs The IDT72V811 is equivalent to two IDT72V211 512 x 9 FIFOs The IDT72V821 is equivalent to two IDT72V221 1,024 x 9 FIFOs The IDT72V831 is equivalent to two IDT72V231 2,048 x 9 FIFOs The IDT72V841 is equivalent to two IDT72V241 4,096 x 9 FIFOs The IDT72V851 is equivalent to two IDT72V251 8,192 x 9 FIFOs ...

Page 2

IDT72V801/72V811/72V821/72V831/72V841/72V851 WENA /LDA 2 WCLKA WENA 1 RSA COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE ...

Page 3

IDT72V801/72V811/72V821/72V831/72V841/72V851 The IDT72V801/72V811/72V821/72V831/72V841/72V851's two FIFOs, referred to as FIFO A and FIFO B, are identical in every respect. The following Symbol Name I Data Inputs Data Inputs RSA, ...

Page 4

... Ind’l) 2.0 — Input Low Voltage (Com’l & Ind’l) — — Operating Temperature 0 — Commercial Operating Temperature -40 Industrial IDT72V801 IDT72V811 IDT72V821 IDT72V831 IDT72V841 IDT72V851 Commercial and Industrial ( 10, 15 CLK Typ. Max. — –1 — 10 — ...

Page 5

... GND to 3.0V 3ns 1.5V 1.5V See Figure 1 5 Com’l & Ind’l Commercial IDT72V801L15 IDT72V801L20 IDT72V811L15 IDT72V811L20 IDT72V821L15 IDT72V821L20 IDT72V831L15 IDT72V831L20 IDT72V841L15 IDT72V841L20 IDT72V851L15 IDT72V851L20 Min. Max. Min. 100 — 66.7 — 6 (1) — 15 — ...

Page 6

IDT72V801/72V811/72V821/72V831/72V841/72V851 FIFO A and FIFO B are identical in every respect. The following description explains the interaction of input and output signals for FIFO A. The correspond- ing signal names for FIFO B are provided in parentheses. Data In (D ...

Page 7

IDT72V801/72V811/72V821/72V831/72V841/72V851 contains four 8-bit offset registers which can be loaded with data on the inputs, or read on the outputs. See Figure 3 for details of the size of the registers and the default values. If FIFO A (B) is ...

Page 8

... Array A (B) is full reads are performed after reset, FFA (FFB) will go LOW after 256 writes to the IDT72V801's FIFO A (B), 512 writes to the IDT72V811's FIFO A (B), 1,024 writes to the IDT72V821's FIFO A (B), 2,048 writes to the IDT72V831's FIFO A (B), 4,096 writes to the IDT72V841's FIFO A (B), or 8,192 writes to the IDT72V851's FIFO A (B) ...

Page 9

IDT72V801/72V811/72V821/72V831/72V841/72V851 RSA (RSB) RENA1, RENA2 (RENB1, RENB2) WENA1 (WENB1) (1) WENA2/LDA (WENB2/LDB) EFA, PAEA (EFB, PAEB) FFA, PAFA (FFA, PAFA ( NOTES: 1. Holding WENA2/LDA (WENB2/LDB) HIGH during reset will ...

Page 10

IDT72V801/72V811/72V821/72V831/72V841/72V851 RCLKA (RCLKB) t ENS RENA1, RENA2 (RENB1, RENB2) EFA (EFB ( OEA (OEB) WCLKA, WCLKB WENA1 (WENB1) WENA2 (WENB2) NOTE: is the minimum time between a rising WCLKA (WCLKB) ...

Page 11

IDT72V801/72V811/72V821/72V831/72V841/72V851 NO WRITE WCLKA (WCLKB) t SKEW1 ( FFA (FFB) WENA1 (WENB1) WENA2 (WENB2) (If Applicable) RCLKA (RCLKB) t ENH t ENS RENA1 (RENB2) OEA LOW (OEB ...

Page 12

... NOTES PAF offset. 2. (256-m) words for the IDT72V801, (512-m) words the IDT72V811, (1,024-m) words for the IDT72V821, (2,048-m) words for the IDT72V831, (4,096-m) words for the IDT72V841, or (8,192-m) words for the IDT72V851. is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for PAFA (PAFB) to change during that clock cycle. If the time between 3 ...

Page 13

IDT72V801/72V811/72V821/72V831/72V841/72V851 t CLK t CLKH WCLKA (WCLKB) LDA (LDB) WENA1 (WENB1 ( PAE OFFSET (LSB) t CLK t CLKH RCLKA (RCLKB) t LDA (LDB) t RENA1, RENA2 (RENB1, RENB2) QA ...

Page 14

IDT72V801/72V811/72V821/72V831/72V841/72V851 SINGLE DEVICE CONFIGURATION — When FIFO A ( Single Device Configuration, the Read Enable 2 RENA2 (RENB2) control input can WCLKA (WCLKB) WENA1 (WENB1) WENA2/LDA (WENB2/LDB Figure 14. Block Diagram of One ...

Page 15

IDT72V801/72V811/72V821/72V831/72V841/72V851 The two FIFOs contained in the IDT72V801/72V811/72V821/72V831/ 72V841/72V851 can be used to prioritize two different types of data shared on a system bus. When writing from the bus to the FIFO, control logic sorts Processor Clock Address Control Data ...

Page 16

... CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 The SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc. The IDT72V801/72V811/72V821/72V831/72V841/72V851 operates in the Depth Expansion configuration when the following conditions are met: 1. WENA2/LDA and WENB2/LDB pins are held HIGH during Reset so that these pins operate as second Write Enables ...

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