ADSP-21065L Analog Devices, ADSP-21065L Datasheet
ADSP-21065L
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ADSP-21065L Summary of contents
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... TWO INDEPENDENT CACHE DUAL-PORTED BLOCKS 32 48 BIT PROCESSOR PORT ADDR DATA ADDR PROGRAM SEQUENCER (MEMORY MAPPED) ALU STATUS, TIMER DATA BUFFERS DSP Microcomputer ADSP-21065L JTAG TEST & EMULATION I/O PORT DATA ADDR ADDR DATA DATA EXTERNAL PORT SDRAM IOD IOA INTERFACE ...
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... ADSP-21065L ...
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... Kbit SRAM memory, host processor interface, DMA con- troller, SDRAM controller, and enhanced serial ports. Figure 1 shows a block diagram of the ADSP-21065L, illustrat- ing the following architectural features: Computation Units (ALU, Multiplier, and Shifter) with a ...
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... The ADSP-21065L is designed to achieve the highest system throughput to enable maximum system performance. It can be clocked by either a crystal or a TTL-compatible clock signal. The ADSP-21065L uses an input clock with a frequency equal to half the instruction rate—a 33 MHz input clock yields processor cycle (which is equivalent to 66 MHz). Inter- faces on the ADSP-21065L operate as shown below. Hereafter in this document input clock frequency, and 2x = processor’ ...
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... Maximum throughput for interprocessor data transfer is 132 Mbytes/sec over the external port. DEVELOPMENT TOOLS The ADSP-21065L is supported with a complete set of software and hardware development tools, including the EZ-ICE Circuit Emulator and development software. The same EZ-ICE hardware that you use for the ADSP-21060/ ADSP-21062 also fully emulates the ADSP-21065L ...
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... ADSP-21065L 10 CLOCK RESET 01 ADSP-21065L #2 CLKIN ADDR 23-0 DATA 31-0 RESET ID 1-0 CONTROL SPORT0 CPA BR SPORT1 ADSP-21065L #1 CS CLKIN ADDR DATA RESET ID ADDR 1-0 23-0 PROCESSOR DATA 31-0 (OPTIONAL) SPORT0 ADDR ACK DATA MS 3-0 BMS ADDR SPORT1 SBTS SW DATA CS HBR CS CONTROL HBG ...
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... PIN DESCRIPTIONS ADSP-21065L pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). Unused inputs should be tied or pulled to VDD or GND, except for ADDR internal pull-up or pull-down resistors (CPA, ACK, DTxX, DRxX, TCLKx, RCLKx, TMS, and TDI)— ...
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... DMA transfers and gain access to the external bus. CPA is an open drain output that is connected to both ADSP-21065Ls in the system. The CPA pin has an internal 5 kΩ pull-up resistor. If core access priority is not required in a system, leave the CPA pin unconnected ...
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... SDRAM. It drives 2x clock out on the SDCLKx pins for the SDRAM interface to use. See also SDCLKx. Connecting the 1x external clock to CLKIN while leaving XTAL unconnected configures the ADSP-21065L to use the external clock source. The instruction cycle rate is equal to 2x CLKIN. CLKIN may not be halted, changed, or operated below the specified frequency. RESET I/A Processor Reset ...
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... O/T SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a host access. XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to enable the ADSP-21065L’s internal clock generator or to disable it to use an external clock source. See CLKIN. PWM_EVENT I/O/A PWM Output/Event Capture. In PWMOUT mode output pin and functions as a timer 1-0 counter ...
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... Connecting CLKIN to Pin 4 of the EZ-ICE header is optional. The emulator only uses CLKIN when directed to perform op- erations such as starting, stopping, and single-stepping two ADSP-21065Ls in a synchronous manner. If you do not need these operations to occur synchronously on the two processors, . The TRST pin must simply tie Pin 4 of the EZ-ICE header to ground ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21065L features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... IDLE16 denotes ADSP-21065L state during execution of IDLE16 instruction. TIMING SPECIFICATIONS General Notes Two speed grades of the ADSP-21065L are offered, 60 MHz and 66 MHz instruction rates. The specifications shown are based on a CLKIN frequency of 30 MHz (t = 33.3 ns). The DT derating allows specifications at other CLKIN frequencies (within the min– ...
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... ADSP-21065L Switching Characteristics specify how the processor changes its signals. You have no control over this timing—circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor will given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device con- nected to the processor (such as memory) is satisfied ...
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... FLAG IN 11–0 CLKIN t SIR t HIR IRQ 2-0 t IPW 1 1 OUT Enable 11-0 OUT Disable 11-0 t DFO t HFO FLAG OUTPUT t HFI t SFI ADSP-21065L Min Max 0.0 6.0 1.0 –5.0 Min Max –2.0 6.0 1.0 –4.0 –4.0 –1.75 t DFO t DFOD Units Units ns ...
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... Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching char- acteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write—Bus Master below). If these tim- ing requirements are met, the synchronous read/write timing can be ignored (and vice versa) ...
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... Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching char- acteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write—Bus Master below). If these tim- ing requirements are met, the synchronous read/write timing can be ignored (and vice versa) ...
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... When accessing a slave ADSP-21065L, these switching characteristics must meet the slave’s timing requirements for synchronous read/writes (see Synchronous Read/Write—Bus Slave). The slave ADSP-21065L must also meet these (bus master) timing require- ments for data and acknowledge setup and hold times. ...
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... CLKIN t DADRO ADDRESS SW ACK (IN) READ CYCLE t DRWL RD DATA (IN) WRITE CYCLE t DRWL WR t DDATO DATA (OUT) t DAAK t SACKC t SSDATI ADSP-21065L t HADRO t HACKC t DRDO t HSDATI t DWRO t DATTR ...
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... ADSP-21065L Synchronous Read/Write—Bus Slave Use these specifications for ADSP-21065L bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor memory space). The bus master must meet these (bus slave) timing requirements. Parameter Timing Requirements: Address, SW Setup Before CLKIN t SADRI ...
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... CLKIN ADDRESS SW t DACK ACK READ ACCESS RD t SDDATO DATA (OUT) WRITE ACCESS WR DATA (IN) t SADRI t HADRI t ACKTR t t SRWLI HRWLI t DATTR t t SRWLI HRWLI t HDATWH t SDATWH ADSP-21065L t RWHPI t RWHPI ...
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... NOTES 1 For first asynchronous access after HBR and CS asserted, ADDR low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the Host Processor Control of the ADSP-21065L section of the ADSP-21065L SHARC User’s Manual, Second Edition. 2 Only required for recognition in the current cycle. ...
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... HBG (OUT) BRx (OUT) CPA (OUT) (O/D) HBG (IN) BRx (IN) CPA (IN) (O/D) HBR CS t DRDYCS REDY (O/D) REDY (A/D) HBG (OUT O/D = OPEN DRAIN, A/D = ACTIVE DRIVE t HHBRI t DHBGO t HHBGO t DBRO t HBRO t DCPAO t SHBGI t SBRI t TRDYHG t HBGRCSV ADSP-21065L t TRCPA t HHBGI t HBRI t ARDYTR ...
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... Use these specifications for asynchronous host processor accesses of an ADSP-21065L, after the host has asserted CS and HBR (low). After the ADSP-21065L returns HBG, the host can drive the RD and WR pins to access the ADSP-21065L’s IOP registers. HBR and HBG are assumed low for this timing. Writes can occur at a minimum interval of (1/2) t ...
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... REDY (O/D) REDY (A/D) WRITE CYCLE ADDRESS CS WR DATA (IN) REDY (O/D) REDY (A/D) O/D = OPEN DRAIN, A/D = ACTIVE DRIVE t SADRDL t SDATRDY t t DRDYRDL RDYPRD t SCSWRL t WWRL t t DRDYWRL RDYPWR ADSP-21065L t HADRDH t WRWH t HDARWH t DRDHRDY t t HADWRH SADWRH t HCSWRH t WRWH t HDATWH t SDATWH t DWRHRDY ...
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... ADSP-21065L Three-State Timing—Bus Master, Bus Slave, HBR, SBTS These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin ...
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... CLKIN SBTS MIENA, MIENS, MIENHG MEMORY INTERFACE t DATEN DATA t ACKEN ACK HBG t MENHBG MEMORY INTERFACE MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, DMAGx. BMS (IN EPROM BOOT MODE) t STSCK t HTSCK MITRA, MITRS, MITRHG t DATTR t ACKTR ADSP-21065L t MTRHBG ...
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... ADSP-21065L DMA Handshake These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate transfers. For hand- shake mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled , RD, WR, SW the ADDR 23-0 ...
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... READ – BUS MASTER,” “MEMORY WRITE – BUS MASTER” AND “SYNCHRONOUS READ/WRITE – BUS MASTER” TIMING SPECIFICATIONS FOR ADDR t DMARLL t WDR t DDGL t SDATDGL t DGWRL t DGWRH t DGRDL t DRDGH t DADGH , RD, WR, SW, MS AND ACK ALSO APPLY HERE. 23–0 3–0 ADSP-21065L t SDRHC t DMARH t HDGC t t WDGL WDGH t DATRDGH t VDATDGH t DATDRH t HDATIDG t DGWRR t DGRDR t ...
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... ADSP-21065L SDRAM Interface—Bus Master Use these specifications for ADSP-21065L bus master accesses of SDRAM. Parameter Timing Requirements: t Data Setup Before SDCLK SDSDK t Data Hold After SDCLK HDSDK Switching Characteristics: t First SDCLK Rise Delay After CLKIN DSDK1 t Second SDCLK Rise Delay After CLKIN ...
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... SSDKC1 SDCLK (IN) t SCSDK 2 CMND (IN) NOTES COMMAND = SDCKE RAS, CAS, SDWE, DQM AND SDA10 SDRAM CONTROLLER ADDS ONE SDRAM CLK THREE-STATED CYCLE DELAY ( t SDKH SDK t t SDKL HDSDK t SDTRSDK t HCADSDK t HCADSDK t SDCTR t SDATR SSDKC2 t HCSDK t / READ FOLLOWED BY A WRITE. CK ADSP-21065L ...
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... ADSP-21065L Serial Ports Parameter External Clock Timing Requirements: t TFS/RFS Setup Before TCLK/RCLK SFSE t TFS/RFS Hold After TCLK/RCLK HFSE t Receive Data Setup Before RCLK SDRE t Receive Data Hold After RCLK HDRE t TCLK/RCLK Width SCLKW t TCLK/RCLK Period SCLK Internal Clock Timing Requirements: t TFS Setup Before TCLK ...
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... TFS t DT DRIVE EDGE TCLK / RCLK DRIVE EDGE TCLK / RCLK t DPTR SPORT ENABLE AND SPORT DISABLE DELAY THREE-STATE FROM INSTRUCTION LATENCY IS TWO CYCLES t DCLK LOW TO HIGH ONLY ADSP-21065L SAMPLE EDGE t SCLKW t DFSE t t HFSE SFSE t t SDRE HDRE SAMPLE EDGE t SCLKW t ...
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... ADSP-21065L EXTERNAL RFS with MCE = 1, MFD = 0 RCLK RFS DT LATE EXTERNAL TFS TCLK TFS DT EXTERNAL RFS with MCE = 1, MFD = 0 RCLK RFS DT LATE EXTERNAL TFS TCLK TFS DT DRIVE SAMPLE DRIVE t t HOFSE/I SFSE DDTE/I DTENLFSE t HDTE/I 1ST BIT t DDTLFSE DRIVE SAMPLE DRIVE t t SFSE/I ...
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... DMAR , RAS, CAS, SDWE, SDCKE, PWM_EVENTx. 0 DMAG2 TCK t t STAP HTAP t DTDO t t DSYS ADSP-21065L Max 11.0 15.0 , IRQ , ID , FLAG , DR0x, DR1x, TCLK0, 2-1 1-0 2-0 11-0 , CPA, FLAG , PWM_EVENTx, DT0x, DT1x, 2-1 11-0 t SSYS HSYS Units ...
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... Example System Hold Time Calculation To determine the data output hold time in a particular system, first calculate the difference between the ADSP-21065L’s output voltage OH 3.1V, +85 C and the input threshold for the device requiring the hold time. A typical ∆ ...
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... LOAD CAPACITANCE – pF 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1 FALL TIME 140 160 180 200 1 0 –1 –2 ADSP-21065L RISE TIME FALL TIME 100 120 140 160 LOAD CAPACITANCE – 100 120 140 160 LOAD CAPACITANCE – pF 180 200 ...
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... Note also that it is not common for an appli- DD cation to have 100% or even 50% of the outputs switching simultaneously. ENVIRONMENTAL CONDITIONS Thermal Characteristics The ADSP-21065L is offered in a 208-lead MQFP and a 196- ball Mini-BGA package. The ADSP-21065L is specified for a case temperature (T × ensure that T used ...
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... FLAG10 120 VDD FLAG9 121 DATA24 FLAG8 122 DATA25 GND 123 DATA26 DATA0 124 VDD DATA1 125 GND DATA2 126 DATA27 ADSP-21065L Pin Pin Pin Pin No. Name No. Name 127 DATA28 169 ADDR17 128 DATA29 170 ADDR16 129 GND 171 ADDR15 130 ...
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... RAS 42 CAS 43 SDWE 44 45 VDD DQM 46 SDCKE 47 SDA10 48 GND 49 DMAG1 50 DMAG2 51 HBG 52 208-LEAD MQFP PIN OO ADSP-21065L TOP VIEW (Not to Scale CONNECT VDD 156 GND 155 154 GND BMS 153 BSEL 152 TCK 151 GND 150 TMS 149 148 TDI 147 TRST ...
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... THE 208 LEAD MQFP IS A METRIC PACKAGE. ENGLISH DIMENSIONS PROVIDED ARE APPROXIMATE AND MUST NOT BE USED FOR BOARD DESIGN PURPOSES. 1.213 (30.80) 1.205 (30.60) SQ 1.197 (30.40) 157 156 1.106 (28.10) 1.102 (28.00) SQ TOP VIEW (PINS DOWN) 1.098 (27.90) 105 104 0.011 (0.27) BSC 0.009 (0.22) 0.007 (0.17) LEAD WIDTH ADSP-21065L ...
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... ADSP-21065L Ball # Name Ball # A1 NC1 B1 A2 NC2 B2 A3 FLAG2 B3 A4 ADDR0 B4 A5 ADDR3 B5 A6 ADDR6 B6 A7 ADDR7 B7 A8 ADDR8 B8 A9 ADDR11 B9 A10 ADDR14 B10 A11 ADDR17 B11 A12 ADDR18 B12 A13 NC8 B13 A14 NC7 B14 F1 TCLK1 G1 F2 DR1B G2 F3 DR1A ...
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... GND GND GND GND VDD DMAG2 VDD VDD VDD VDD VDD DATA2 FLAG10 ACK CPA RD MS1 DATA1 FLAG11 GND REDY MS3 MS2 MS0 SW FLAG9 ADSP-21065L FLAG2 NC2 NC1 IRQ0 B RFS0 DR0A C IRQ2 RCLK0 TCLK0 D IRQ1 DR0B TFS0 RCLK1 E RFS1 DT0A DT0B ...
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... ADSP-21065L Part Case Temperature Number Range ADSP-21065LKS-240 0°C to +85°C ADSP-21065LCS-240 –40°C to +100°C ADSP-21065LKCA-240 0°C to +85°C ADSP-21065LKS-264 0°C to +85°C ADSP-21065LKCA-264 0°C to +85°C 15.20 15.00 SQ 14.80 TOP VIEW TOP VIEW 1.90 1.75 1.60 CCC = 0.25 (TOP PLANARITY) ...